由於浮動式閘極快閃記憶體無法滿足元件微縮發展的趨勢，因此利用電荷陷阱式快閃記憶體式取代浮動式閘極結構元件是未來發展的趨勢。然而SONOS元件其一穿遂氧化層厚度則大約是30A，就這樣的厚度而言，對於元件在可靠度方面的品質來說就會是一個問題，亦即，要如何在不改變穿遂氧化層厚度的前提之下，仍然能夠讓元件具有十年以上的電荷留存能力?並且在不犧牲資料留存能力的要求下在電性方面能有所提升，這些都是目前急需克服的問題。其二以氮化矽做為電荷儲存層的結構，在發展到次微米以下時就無法再以降低穿隧氧化層厚度的方式來提升元件操作效率，因此便引進了高介電材料來取代傳統ONO結構以提升元件操作特性，但此時面臨到的將是抹除速度與電荷保持力之間的trade-off問題。
本實驗其一將利用不同高介電係數材料以堆疊方式堆疊出SONOS元件的阻擋氧化層，研究主要是利用不同的材料具有不同的特性，配合堆疊式的結構、能隙大小的改變，K值的影響，堆疊厚度的改變等種種原因，利用能帶工程堆疊出最恰當的阻擋氧化層。本實驗其二將利用不同高介電係數的材料與氮化矽搭配，以堆疊的方式堆疊出電荷儲存層。研究主要是利用不同材料具有不同的特性，配合堆疊的結構，藉著電荷陷阱密度的多寡、能階大小的改變、K值影響分壓的不同、陷阱能階等種種特性，配合能帶工程堆疊出最佳特性的電荷儲存層。
實驗結果可發現，引進能帶工程，各別利用對阻擋氧化層與電荷儲存層的特性，堆疊出適當的結構，將有助於提升元件的效能，寫入/抹除/電荷保持力。

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