研究生: |
王嗣裕 Szu-Yu Wang |
---|---|
論文名稱: |
能帶隙工程矽-氧-氮-氧-矽快閃記憶體元件之可靠度與製程效應研究 Reliability and Processing Effects of Bandgap Engineered SONOS (BE-SONOS) Flash Memory Devices |
指導教授: |
龔正
Jeng Gong |
口試委員: | |
學位類別: |
博士 Doctor |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2008 |
畢業學年度: | 96 |
語文別: | 英文 |
論文頁數: | 106 |
中文關鍵詞: | 能 、矽-氧-氮-氧-矽 元件 、氧-氮-氧 穿隧介電層 、製程效應 、可靠度 、快閃記憶體 |
外文關鍵詞: | Bandgap Engineering, SONOS, ONO Tunneling Dielectric, Processing Effect, Reliability, Flash Memory |
相關次數: | 點閱:1 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
Charge-trapping memory devices are forecasted to be the solution for Flash memory beyond 40 nm node. SONOS device that introduced in late 1960’s is one type of charge-trapping memory devices in which charges are trapped in silicon nitride material. However, the conventional SONOS has a fundamental limitation that there is no suitable thickness for tunnel oxide to achieve good erase speed and data retention performance at the same time.
Recently, a new charge-trapping Flash memory device named bandgap engineered SONOS (BE-SONOS) is proposed to overcome the fundamental limitation of SONOS. With the help of bandgap engineering in the very thin ONO tunneling barrier (typical of 13/20/25 Å for O1/N1/O2), the band-offset under high electric field can reduce the hole tunneling distance effectively because the O1 is almost the only effective tunneling barrier and thus a large hole current is allowed. On the other hand, at low electric field during retention, both electron de-trapping and hole direct tunneling are completely prohibited by the total barrier thickness (O1+N1+O2).
In this thesis a more detailed understanding of BE-SONOS reliabilities is given including the device concept, processing effects on different dielectric layers, effect of charge-trapping layer engineering, and the capability of dielectric scaling. From the results in confidence, we believe BE-SONOS is so far the best choice of charge-trapping memory devices on the next-generation applications of non-volatile semiconductor memory (NVSM), especially for NAND Flash memory.
電荷捕捉記憶體元件預期將成為快閃記憶體於40奈米以下世代產品的解決方案。於1960年代末期發明之矽-氧-氮-氧-矽(SONOS)元件就是其中一種型態的電荷捕捉記憶體元件。該種元件是將電荷儲存在氮化矽材料當中。然而,傳統的SONOS記憶體元件存在著一種應用上的限制,就是我們無法找到一個合適的穿隧氧化層厚度來同時達到優良的抹除速度以及資料保存能力。
最近這幾年一種新的電荷捕捉快閃記憶體元件被提出具有克服傳統SONOS元件應用上限制的能力。該種記憶體元件稱作能帶隙工程矽-氧-氮-氧-矽(BE-SONOS)元件。在採用非常薄的氧-氮-氧穿隧阻障層(一般來說各層厚度約在13/20/25 埃)的情況下,高電場下的電荷穿隧距離會因為能帶隙消除效應而有效降低。此時幾乎僅存第一層超薄氧化層扮演有效之電荷穿隧障礙,因此大大提高了電洞穿隧電流。另一方面當電荷儲存狀態的低電場條件下,不論電子自儲存層中逸失或是電洞穿隧進入儲存層之能力皆會因為整個氧-氮-氧穿隧阻障層的阻擋而顯著降低。
本論文將針對此新開發的BE-SONOS記憶體元件在基本元件概念、各介電層之製程效應、電荷捕捉層工程效應、以及介電層微縮能力在可靠度特性上之研究提供詳細的說明。從這些研究結果我們認為在次世代的非揮發性記憶體,特別是資料儲存式快閃記憶體(NAND Flash)的應用上,BE-SONOS是目前電荷捕捉記憶體元件當中的最佳解決方案。
[1] H. Wegener, A. Lincoln, H. Pao, M. O’Connell, and R. Oleksiak, “The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device”, International Electron Devices Meeting, 1967, p. 70
[2] D. Frohman-Bentchkowsky, “The metal-nitride-oxide-silicon (MNOS) transistor – Characteristics and applications, Proceedings of the IEEE, vol. 58, 1970, pp. 1207-1219
[3] M. White, D. Adams, and J. Bu, “On the go with SONOS”, IEEE Circuits and Designs, 2000, pp. 22-31
[4] G. Servalli, D. Brazzelli, E. Camerlenghi, G. Capetti, S. Costantini, C. Cupeta, D. DeSimone, A. Ghetti, T. Ghilardi, P. Gulli, M. Mariani, A. Pavan, and R. Somaschini, “A 65nm NOR flash technology with 0.042mm2 cell size for high performance multilevel application”, International Electron Devices Meeting (IEDM), 2005, pp. 849-852
[5] D. Kang, S. Jang, K. Lee, J. Kim, H. Kwon, W. Lee, B. G. Park, J. D. Lee, and H. Shin, “Improving the cell characteristics using low-k gate spacer in 1Gb NAND flash memory”, International Electron Devices Meeting (IEDM), 2006, pp. 1001-1004
[6] M. Noguchi, T. Yaegashi, H. Koyama, M. Morikado, Y. Ishibashi, S. Ishibashi, K. Ino, K. Sawamura, T. Aoi, T. Maruyama, A. Kajita, E. Ito, M. Kishida, K. Kanda, K. Hosono, S. Miyamoto, F. Ito, Y. Hirata, G. Hemink, M. Higashitani, A. Mak, J. Chan, M. Koyanagi, S. Ohshima, H. Shibata, H. Tsunoda and S. Tanaka, “A high-performance multi-level NAND Flash memory with 43nm-node floating-gate technology”, International Electron Devices Meeting (IEDM), 2007, pp. 445-448
[7] K. Kim and J. Choi, “Future outlook of NAND flash technology for 40nm node and beyond”, 21st Non-Volatile Semiconductor Memory Workshop (NVSMW), 2006, pp. 34-35
[8] K. Kim, “Memory technologies for 50 nm and beyond”, 8th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2006, pp. 685-688.
[9] J. Kim, J. D. Choi, W. C. Shin, D. J. Kim, H. S. Kim, K. M. Mang, S. T. Ann, and O. H. Kwon, “Scaling down of tunnel oxynitride in NAND flash memory: oxynitride selection and reliabilities”, 35th Proceedings of IEEE International Reliability Physics Symposium (IRPS), 1997, pp 12-16
[10] T. Ogata, M. Inoue, T. Nakamura, N. Tsuji, K. Kobayashi, K. Kawase, H. Kurokawa, T. Kaneoka, Y. Ohno, and H. Miyoshi, “Impact of nitridation engineering on microscopic SILC characteristics of sub-10-nm tunnel dielectrics”, International Electron Devices Meeting (IEDM), 1998, pp. 597-600
[11] J. G. Lee, W. H. Kwon, W. Lee, J. H. Park, H. K. Kim, H. M. Son, W. J. Chang, J. J. Han, Y. W. Hyung, and H. D. Lee, “Development and optimization of re-oxidized tunnel oxide with nitrogen incorporation for the Flash memory applications”, 45th Proceedings of IEEE International Reliability Physics Symposium (IRPS), 2007, pp. 184-189
[12] S. Mori, Y. Y. Araki, M. Sato, H. Meguro, H. Tsunoda, E. Kamiya, K. Yoshikawa, N. Arai, and E. Sakagami, “Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices”, IEEE Transactions on Electron Devices, vol. 43, no. 1, Jan., 2005, pp. 47-53
[13] H. T. Lue, Y. H. Shih, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Novel soft erase and re-fill methods for a P+-poly gate nitride-trapping non-volatile memory device with excellent endurance and retention properties”, 43th Proceedings of IEEE International Reliability Physics Symposium (IRPS), 2005, pp. 168-174
[14] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: A novel localized Trapping, 2-Bit Nonvolatile Memory Cell”, IEEE Electron Device Letters, 2000, pp. 543-545.
[15] C. H. Lee, K. I. Choi, M. K. Cho, Y. H. Song, K. C. Park, and K. Kim, “A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit flash memories”, International Electron Device Meeting (IEDM), 2003, pp. 613-616.
[16] H. T. Lue, S. Y. Wang, E. K. Lai, Y. H. Shih, S. C. Lai, L. W. Yang, K. C. Chen, J. Ku, K. Y. Hsieh, R. Liu, and C. Y. Lu, “BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability”, International Electron Devices Meeting (IEDM), 2005 pp. 547-550
[17] H. T. Lue, S. Y. Wang, E. K. Lai, M. T. Wu, L. W. Yang, K. C. Chen, J. Ku, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A novel p-channel NAND-type Flash memory with 2-bit/cell operation and high programming throughput (>20 MB/sec),” International Electron Devices Meeting (IEDM), 2005, pp. 331-334
[18] H. T. Lue, S. Y. Wang, Y. H. Hsiao, E. K. Lai, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Reliability model of bandgap engineered SONOS (BE-SONOS)”, International Electron Device Meeting (IEDM), 2006, pp. 495-498
[19] E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, S. C. Lee, C. P. Lu, S. Y. Wang, L. W. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, J. Ku, R. Liu, and C. Y. Lu, “A highly stackable Thin-Film Transistor (TFT) NAND-type Flash memory”, International Symposium on VLSI Technology, 2006, pp. 56-57
[20] E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, S. C. Lee, C. P. Lu, S. Y. Wang, L. W. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, J. Ku, R. Liu, and C. Y. Lu, “A multi-layer stackable Thin-Film Transistor (TFT) NAND-type Flash memory”, International Electron Devices Meeting (IEDM), 2006, pp. 41-44
[21] H. T. Lue, S. Y. Wang, E. K. Lai, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A BE-SONOS (Bandgap Engineered SONOS) NAND for post-floating gate era Flash memory”, International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2007, pp. 16-17
[22] S. C. Lai, H. T. Lue, J. H. Hsieh, M. J. Yang, Y. K. Chiou, C. W. Wu, T. B. Wu, G. L. Luo, C. H. Chien, E. K. Lai, K. Y. Hsieh, R. Liu, and C.Y. Lu, “A study on the erase and retention mechanisms for MONOS, MANOS, and BE-SONOS non-volatile memory devices”, International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2007, pp. 14-15
[23] H. T. Lue, T. H. Hsu, S. Y. Wang, Y. H. Hsiao, E. K. Lai, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Study of local trapping and STI edge effects on Charge-Trapping NAND Flash”, International Electron Devices Meeting (IEDM), 2007, pp. 161-164
[24] T. H. Hsu, H. T. Lue, E. K. Lai, J. Y. Hsieh, S. Y. Wang, L. W. Yang, Y. C. King, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A high-speed BE-SONOS NAND Flash utilizing the field-enhancement effect of FinFET”, International Electron Devices Meeting (IEDM), 2007, pp. 913-916
[25] H. T. Lue, E. K. Lai, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A novel gate-injection program/erase p-channel NAND-type Flash memory with high (10M cycle) endurance”, International Symposium on VLSI Technology, 2007, pp. 140-141
[26] H. T. Lue, T. H. Hsu, S. Y. Wang, E. K. Lai, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Study of incremental step pulse programming (ISPP) and STI edge effect of BE-SONOS NAND Flash”, 46th Proceedings of IEEE International Reliability Physics Symposium (IRPS), 2008, pp. 693-694
[27] S. C. Lai, H. T. Lue, C. W. Liao, T. B. Wu, M. J. Yang, Y. H. Lue, J. Y. Hsieh, S. Y. Wang, G. L. Luo, C. H. Chien, K. Y. Hsieh, R. Liu and C. Y. Lu, “Highly reliable MA BE-SONOS (Metal-Al2O3 bandgap engineered SONOS) using a SiO2 buffer layer”, International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2008, pp. 62-63
[28] H. T. Lue, T. H. Hsu, S. C. Lai, Y. H. Hsiao, W. C. Peng, C. W. Liao, Y. F. Huang, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Scaling evaluation of BE-SONOS NAND Flash beyond 20 nm”, International Symposium on VLSI Technology, 2008, pp.116-117
[29] H. T. Lue, E. K. Lai, Y. H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A novel junction-free BE-SONOS NAND Flash”, International Symposium on VLSI Technology, 2008, pp.140-141
[30] Z. L. Huo, J. K. Yang, S. H. Lim, S. J. Baik, J. Lee, J. H. Han, I. S. Yeo, U. I. Chung, J. T. Moon, and B. I. Ryu, “Band engineered charge trap layer for highly reliable MLC Flash memory”, International Symposium on VLSI Technology, 2007, pp.138-139
[31] Y. Q. Wang, D. Y. Gao, W. S. Hwang, C. Shen, G. Zhang, G. Samudra, Y. C. Yeo, and W. J. Yoo, “Fast erasing and highly reliable MONOS type memory with HfO2 high-k trapping layer and Si3N4/SiO2 tunneling stack”, International Electron Devices Meeting (IEDM), 2006, pp. 971-974
[32] Y. J. Ahn, J. Choe, J. J. Lee, D. Choi, E. S. Cho, B. Y. Choi, S. Lee, S. Sung, C. Lee, S. H. Cheong, D. K. Lee, S. B. Kim, D. Park, and B. Ryu, “Trap layer engineered FinFET NAND Flash with enhanced memory window”, International Symposium on VLSI Technology, 2006, pp. 88-89
[33] K. H. Wu, H. C. Chien, C. C. Chan, T. S. Chen, and C. H. Kao, “SONOS devices with tapered bandgap nitride layer”, IEEE Transactions on Electron Devices, vol. 52, no. 5, 2005, pp. 987-992
[34] H. T Lue, P. Y. Du, S. Y. Wang, E. K. Lai, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A novel gate-sensing and channel-sensing transient analysis method for real-time monitoring of charge vertical location in SONOS-type devices and its applications in reliability studies”, 45th Proceedings of IEEE International Reliability Physics Symposium (IRPS), 2007, pp. 177-183
[35] S. K. Sung, I. H. Park, C. J. Lee, Y. K. Lee, J. D. Lee, B. G. Park, S. D. Chae, and C. W. Kim, “Fabrication and program/erase characteristics of 30-nm SONOS nonvolatile memory devices”, IEEE Transactions on Nanotechnology, vol. 2, 2003, pp. 258-264
[36] K. T. Chang, W. M. Chen, C. Swift, J. Higman, W. Paulson, and K. M. Chang, “A new SONOS memory using source-side injection for programming”, IEEE Electron Device Letters, vol. 19, 1998, pp. 253-255
[37] H. T. Lue, T. H. Hsu, M. T. Wu, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model”, IEEE Transactions on Electron Devices, vol. 53, no. 1, 2006, pp. 119-125
[38] W. J. Tsai, N. K. Zous, C. C. Yeh, C. C. Liu, C. H. Chen, T. Wang, S. Pan, and C. Y. Lu, “Cause of data retention loss in a nitride-based localized trapping storage flash memory cell”, 40th Proceedings of International Reliability Physics Symposium (IRPS), 2002, pp. 34-38
[39] T. Wang, W. J. Tsai, S. H. Gu, C. T. Chan, C. C. Yeh, N. K. Zous, T. C. Lu, S. Pan, and C. Y. Lu, “Reliability models of data retention and read-disturb in 2-bit nitride storage flash memory cells”, International Electron Devices Meeting (IEDM), 2003, pp. 169-172
[40] Y. H. Shih, S. C. Lee, H. T. Lue, M. D. Wu, T. H. Hsu, E. K. Lai, J. Y. Hsieh, C. W. Wu, L. W. Yang, K. Y. Hsieh, K. C. Chen, R. Liu, and C. Y. Lu, “Highly reliable 2-bit/cell nitride trapping flash memory using a novel array-nitride-sealing (ANS) ONO process”, International Electron Devices Meeting (IEDM), 2005, pp. 559-562
[41] Y. H. Shih, E. K. Lai, J. Y. Hsieh, T. H. Hsu, M. D. Wu, C. P. Lu, K. P. Ni, T. Y. Chou, L. W. Yang, K. Y. Hsieh, M. H. Liao, W. P. Lu, K. C. Chen, J. Ku, F. L. Ni, R. Liu, and C. Y. Lu, “Highly scalable and reliable multi-bit/cell nitride trapping nonvolatile memory using enhanced ANS-ONO process with a nitridized interface”, International Electron Devices Meeting (IEDM), 2006, pp. 503-506
[42] Y. Park, J. Choi, C. Kang, C. Lee, Y. Shin, B. Choi, J. Kim, S. Jeon, J. Sel, J. Park, K. Choi, T. Yoo, J. Sim, and K. Kim, “Highly manufacturable 32Gb multi-level NAND flash memory with 0.0098 μm2 cell size using TANOS (Si-Oxide-Al2O3-TaN) cell technology”, International Electron Device Meeting (IEDM), 2006, pp. 29-32
[43] C. H. Lee, J. Choi, C. Kang, Y. Shin, J. S. Lee, J. Sel, J. Sim, S. Jeon, B. I. Choe, D. Bae, K. Park, and K. Kim, “Multi-level NAND flash memory with 63 nm-node TANOS (Si-Oxide-SiN-Al2O3-TaN) cell structure”, International Symposium on VLSI Technology, 2006, pp. 21-22
[44] High-k gate dielectric short course, 44th Proceedings of International Reliability Physics Symposium (IRPS), 2006
[45] K. K. Likharev, “Layered tunnel barriers for non-volatile memory”, Applied Physic Letters, 1998, pp. 2137-2139
[46] H .T. Lue, Y. H. Shih, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A transient analysis method to characterize the trap vertical location in nitride-trapping devices”, IEEE Electron Device Letters, vol. 25, 2004, pp.816-818
[47] V. A. Gritsenko, Y. N. Morokov, Y. N. Novikov, I. P. Petrenko, S. N. Svitasheva, H. Wong, R. Kwok, and R. Chen, “Characterization of the silicon nitride - thermal oxide interface in ONO structures by ELS, XPS, ellipsometry, and numerical simulation”, Proceedings of 21st International Conference on Microelectronics (MIEL), vol. 1, 1997, pp. 14-17
[48] E. Suzuki, Y. Hayashi, K. Ishii, and T. Tsuchiya, “Traps created at the interface between the nitride and the oxide on the nitride by thermal oxidation”, Applied Physics Letters, vol. 42, 1983, pp. 608-610
[49] T. Ishida, Y. Okuyama, and R. Yamada, “Characterization of charge traps in metal-oxide-nitride-oxide-semiconductor (MONOS) structures for embedded Flash memories”, 44th Proceedings of International Reliability Physics Symposium (IRPS), 2006, pp. 516-522
[50] A. Arreghini, F. Driussi, D. Esseni, L. Selmi, M.J. van Duuren, and R. van Schaijk, “Experimental extraction of the charge centroid and of the charge type in the P/E operation of SONOS memory cells”, International Electron Devices Meeting (IEDM), 2006, pp. 1-4
[51] S. M. Sze, Physics of semiconductor devices, 2nd ed. New York: Wiley, 1983
[52] P. Y. Du, H. T. Lue, S. Y. Wang, E. K. Lai, T. Y. Huang, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Study of the erase mechanism of charge-trapping devices using the gate-sensing and channel-sensing transient analysis: Hole injection or electron de-trapping?”, 46th Proceedings of International Reliability Physics Symposium (IRPS), 2008, pp. 399-405
[53] S. J. Wrazien, Y. Zhao, J. D. Krayer and M. H. White, “Characterization of SONOS oxynitride nonvolatile semiconductor memory devices”, Solid-State Electronics, vol. 47, 2003, pp 885-891