本篇論文的重點在於反摻雜接面終結延伸應用於高電壓(>10kV)垂直型碳化矽元件的研究。根據模擬，單一區JTE結構的崩潰電壓對於JTE劑量變化相當敏感。反摻雜接面終結延伸區域為藉由佈植Ⅴ族元素在p型JTE，逐漸地減少JTE從內到外的濃度以形成多區域JTE的效果，使得電場被更均勻地分散，加寬佈植劑量的窗口和增加崩潰電壓。

本次實驗選用4H-碳化矽基板以及厚度為110µm、濃度為6.5x1014cm-3的磊晶層。以各種邊緣終結保護結構佈植不同的JTE的劑量，目標是達到崩潰電壓大於10kV以上。透過陽極歐姆接觸前的RIE製程改善，在順向偏壓10V時，電流密度可達到800A/cm2，反向特性方面，當反摻雜接面終結延伸長度為300µm時，6CD-JTE+OR的結構其崩潰電壓可以達到大於3000V，然而當反摻雜接面終結延伸長度為240µm時，其崩潰電壓不如模擬預期中的高，因此反摻雜結構在模擬和實驗之間的差異需要更進一步的查證。

Counter-doped junction termination extension (CD-JTE) for high-voltage (> 10kV) vertical SiC devices is investigated in this thesis. From simulation, breakdown voltage is very sensitive to the variation of JTE dose in SZ-JTE structure. In CD-JTE, N-type implant in the p-type JTE region, which reduces the effective JTE dose, can create a multi-zone effect. It makes electric field more uniformly distributed in the depleted JTE region to widen the process window of JTE dose and enhance breakdown voltage.

In experiment, a 110-µm-thick n-type epilayer with a doping concentration of 6.5x1014cm-3 was grown on a 4H-SiC substrate. Several edge terminations with different JTE doses were fabricated in order to achieve breakdown voltage greater than 10kV. The measured forward voltage drop at 800A/cm2 is 10V. In reverse characteristics, the breakdown voltage achieved with a 300µm wide 6CD-JTE+OR is more than 3000V. However, when CD-JTE width is reduced to 240µm, the breakdown voltage is not as high as predicted by simulation. The discrepancies between simulation and experiment require further examination.

[1] H. Matsunami, T. Kimoto, “Step-controlled epitaxial growth of SiC: High quality homoepitaxy,” Materials Science and Engineering: R: Reports, vol. 20, Issue 3, pp. 125-166, 1997.
[2] A. R. Powell and L. B. Rowland, "SiC materials-progress, status, and potential roadblocks," Proceedings of the IEEE, vol. 90, no. 6, pp. 942-955, Jun 2002.
[3] M. Bhatnagar and B. J. Baliga, “Comparison of 6H-SiC, 3C-SiC, and Si for power devices,” IEEE Transactions on Electron Devices, vol. 40, no. 3, pp. 645–655, Mar. 1993.
[4] B. J. Baliga, “Fundamentals of Power Semiconductor Devices,” 2008.
[5] M. C. Tarplee, V. P. Madangarli, and Q. Zhang, “Design rules for field plate edge termination in SiC Schottky diodes,” IEEE Transactions on Electron Devices, vol. 48, no. 12, pp. 2659-2664, Dec. 2001.
[6] A. W. Ludikhuize, “A review of RESURF technology,” International Symposium on Power Semiconductor Devices and ICs, pp.11-18, 2000.
[7] R. Perez, D. Tournier, A. Perez-Tomas, P. Godignon, N. Mestres and J. Millan, “Planar edge termination design and technology considerations for 1.7-kV 4H-SiC PiN diodes,” IEEE Transactions on Electron Devices, vol. 52, no. 10, pp. 2309-2316, Oct. 2005.
[8] E. A. Imhoff et al., “High-performance smoothly tapered junction termination extensions for high-voltage 4H-SiC devices,” IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3395-3400, Oct. 2011.
[9] W. Sung, E. Van Brunt, B. J. Baliga and A. Q. Huang, “A new edge termination technique for high-voltage devices in 4H-SiC–multiple-floating-zone junction termination extension,” IEEE Electron Device Letters, vol. 32, no. 7, pp. 880-882, July 2011.
[10] H. Niwa, G. Feng, J. Suda, and T. Kimoto, “Breakdown characteristics of 15-kV-class 4H-SiC PiN diodes with various junction termination structures,” IEEE Transactions on Electron Devices, vol. 59, no. 10, pp. 2748–2752, Oct. 2012.
[11] H. Niwa, G. Feng, J. Suda and T. Kimoto, “Breakdown characteristics of 12–20 kV-class 4H-SiC PiN diodes with improved junction termination structures,” 2012 24th International Symposium on Power Semiconductor Devices and ICs, Bruges, pp. 381-384, 2012.
[12] S. H. Ryu, S. Krishnaswami, B. Hull, J. Richmond, A. Agarwal, and A. Hefner, “10 kV, 5A 4H-SiC power DMOSFET,” Proceedings of the 18th International Symposium on Power Semiconductor Devices & IC's, pp. 1–4, Jun. 2006.
[13] J. H. Zhao, P. Alexandrov, and X. Li, “Demonstration of the first 10-kV 4H-SiC Schottky barrier diodes,” IEEE Electron Device Letters, vol. 24, no. 6, pp. 402–404, Jun. 2003.
[14] H. Miyake, T. Okuda, H. Niwa, T. Kimoto and J. Suda, “21-kV SiC BJTs with space-modulated junction termination extension,” IEEE Electron Device Letters, vol. 33, no. 11, pp. 1598-1600, Nov. 2012.
[15] H. Niwa, J. Suda, and T. Kimoto, “21.7 kV 4H-SiC PiN diode with a space-modulated junction termination extension,” Applied Physics Express, vol. 5, no. 6, p. 064001, May 2012.
[16] C. F. Huang et al., “Counter-doped JTE, an edge termination for HV SiC devices with increased tolerance to the surface charge,” IEEE Transactions on Electron Devices, vol. 62, no. 2, pp. 354-358, Feb. 2015.
[17] J. Y. Jiang, H. C. Hsu, K. W. Chu, C. F. Huang and F. Zhao, "Experimental study of counter-doped junction termination extension for 4H–SiC power devices," IEEE Electron Device Letters, vol. 36, no. 7, pp. 699-701, July 2015.
[18] A. O. Konstantinov, Q.Wahab, N. Nordell, and U. Lindefeltd, “Ionization rates and critical fields in 4H silicon carbide,” Applied Physics Letters, vol. 71, no. 1, pp. 90–92, 1997.
[19] H. Lendenmann, A. Mukhitdinov, F. Dahlquist, H. Bleichner, M. Irwin and R. Soderholm, “4.5 kV 4H-SiC diodes with ideal forward characteristic,” Power Semiconductor Devices and ICs, 2001. ISPSD '01. Proceedings of the 13th International Symposium on, Osaka, pp. 31-34, 2001.
[20] K. P. Schoen, J. M. Woodall, J. A. Cooper and M. R. Melloch, “Design considerations and experimental analysis of high-voltage SiC Schottky barrier rectifiers,” IEEE Transactions on Electron Devices, vol. 45, no. 7, pp. 1595-1604, Jul. 1998.
[21] Y. Negoro, K. Katsμmoto, T. Kimoto and H. Matsunami, “Electronic behaviors of high-dose phosphorus-ion implanted 4H-SiC(0001),” Journal of Applied Physics, vol. 96, no. 1, pp. 224-228, 2004.
[22] D. Neamen, “An Introduction to Semiconductor Devices,” 2006.
[23] T. Hiyoshi, T. Hori, J. Suda and T. Kimoto, “Simulation and experimental study on the junction termination structure for high-voltage 4H-SiC PiN diodes,” IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 1841-1846, Aug. 2008.
[24] S. Sundaresan, M. Marripelly, S. Arshavsky and R. Singh, “15 kV SiC PiN diodes achieve 95% of avalanche limit and stable long-term operation,” 2013 25th International Symposium on Power Semiconductor Devices & IC's, Kanazawa, pp. 175-177, 2013.
[25] S. Sundaresan, C. Sturdevant, M. Marripelly, E. Lieser and R. Singh, “12.9 kV SiC PiN diodes with low on-state drops and high carrier lifetimes,” Materials Science Forum, vol.717-720, pp.949-952, May 2012.