低雜訊動態電路之合成｜國立清華大學博碩士論文庫

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研究生：	劉一宇 Yi-Yu Liu
論文名稱：	低雜訊動態電路之合成 Crosstalk-aware Synthesis for Dynamic Circuit
指導教授：	黃婷婷 Ting-Ting Hwang
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	96
中文關鍵詞：	雜訊、效能、邏輯合成、技術映成、動態電路、骨牌電路、繞線
外文關鍵詞：	crosstalk, performance, logic synthesis, technology mapping, dynamic circuit, domino circuit, routing
相關次數：	點閱：3 下載：0
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低雜訊電路設計已成近年來超大型積體電路設計的重要研究議題，隨著晶片製成技術高速的進展，單位面積所能容納的半導體數目每十八個月即增加一倍，半導體內部元件亦隨之縮小。隨著導線距離降低，耦合電容所造成之電磁效應亦倍增，伴隨而來的雜訊將導致電路效能降低、功率消耗增加，甚至造成電路故障。因此，低雜訊的設計成為當今超大型積體電路重要的發展趨勢。

在本篇論文中，我們從探討動態可程式化邏輯陣列特性出發，接下來，我們展現一些合成低雜訊動態可程式化邏輯陣列的方法。藉由改變輸入、輸出及乘積的路線，我們進一步地得到低雜訊動態可程式化邏輯陣列。實驗結果顯示，我們可以降低51%之耦合電容，有效減少動態可程式化邏輯陣列之雜訊。

接下來，我們提出低雜訊動態電路的邏輯合成方法，藉由我們所提出的技術映成演算法，我們可以合成出低雜訊之動態電路邏輯閘，進而大幅度降低導線之間的雜訊。實驗結果顯示，在完成電路佈局及繞線後，我們可以將繞線間之耦合電容降低至原本的60%。如此一來，電路的雜訊將可以大幅度降低。

最後，我們提出低雜訊動態電路的繞線演算法，藉由找出電路裡的關鍵路徑，我們將較佳的繞線資源提供給關鍵路徑，使電路的效能得以進一步提升。實驗結果顯示，我們可以減少4.7%之關鍵路徑延遲，同時可以再降低繞線間17%之耦合電容。不但能夠減少電路因為雜訊而造成錯誤的機會，還能夠進一步提升整體電路的效能。

Crosstalk effect results in performance degradation and at worst gives incorrect result in contemporary VLSI manufacturing. In this dissertation, we present a new perspective on high performance domino circuit design taking crosstalk effect into consideration.

In the first part, we propose a maximum crosstalk effect minimization algorithm, taking logic synthesis into consideration for PLA structures. To minimize the crosstalk effect, a technique of permuting wire is used, which contains the following steps. First, product terms are partitioned into a long set and a short set, and then product terms in the long and short sets are interleaved. After that, we take advantage of the crosstalk immunity of product terms in the long set to further reduce the maximum coupling capacitance of the PLA. Finally, synthesis techniques such as local transformation and global transformation are taken into consideration to search for a better result. The experiments demonstrate that our algorithm can effectively minimize the maximum coupling capacitance of a circuit by 51% as compared with the original area-minimized PLA without crosstalk effect minimization.

In the second part, we propose a logic synthesis flow to synthesize a domino-cell network with less crosstalk effect. Crosstalk immunity property of OR gate and relations between wire adjacency and cell I/O are exploited in technology mapping. Meanwhile, metric to measure the crosstalk sensitivity of domino cells in synthesis level is proposed. Experimental results demonstrate that the crosstalk sensitivity of the synthesized domino-cell network is greatly reduced by 52% using our synthesis flow as compared with conventional methodology. Furthermore, after placement and routing are performed, the ratio of the number of crosstalk-immune wire pairs to the number of total wire pairs is about 24% using our methodology as compared to 9\% using conventional techniques and the maximum wire coupling can be greatly reduced from 95% to 60%.

In the last part, we propose a routing algorithm taking crosstalk immunity into consideration. The crosstalk immunity relation computed during technology mapping is utilized to reduce the crosstalk effect during wire routing. First, via number estimation and wire couple estimation are proposed to estimate the criticality precisely. Then, we present a path-based routing framework to route critical or near-critical nets first. Finally, crosstalk-avoidance rerouting is performed to reduce crosstalk coupling. The experimental result shows that the circuit delay routed by our performance-driven router is 4.7% less than that routed by MR. After initial routing, our crosstalk-avoidance rerouting can reduce 17% of the maximum wire coupling on critical wires.

Introduction 1
1 CrosstalkMinimization for Dynamic PLA . . . . . . . . . . . . . . . . 2
2 CrosstalkMinimization in TechnologyMapping . . . . . . . . . . . . . 3
3 Crosstalk-aware Routing . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Dissertation Organization . . . . . . . . . . . . . . . . . . . . . . . . . 4
Literature Review 6
1 NoiseMinimization in Domino Circuit . . . . . . . . . . . . . . . . . . 6
2 CrosstalkMinimization in Physical Level . . . . . . . . . . . . . . . . . 7
2.1 Performance-driven Placement . . . . . . . . . . . . . . . . . . . 7
2.2 Performance-driven Routing . . . . . . . . . . . . . . . . . . . . 8
Preliminary 9
1 Unateness of Domino Circuit . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Crosstalk Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Crosstalk Minimization for Dynamic PLA 12
1 PLA Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Motivation of PLA CrosstalkMinimization . . . . . . . . . . . . . . . . 14
2.1 Crosstalk Effect on Dynamic PLA . . . . . . . . . . . . . . . . . 14
iii
2.2 Crosstalk Formulation for Dynamic PLA . . . . . . . . . . . . . 17
2.3 Example of PLA CrosstalkMinimization . . . . . . . . . . . . . 18
3 Flow Chart of PLA Crosstalk Minimization Algorithm . . . . . . . . . 21
4 PLA CrosstalkMinimization . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 Initial I/O Ordering . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Long Set and Short Set Interleaving . . . . . . . . . . . . . . . . 24
4.3 Grouping in Long Set . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4 I/O Re-ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5 Proof of Correctness . . . . . . . . . . . . . . . . . . . . . . . . 31
5 Synthesis for CrosstalkMinimization . . . . . . . . . . . . . . . . . . . 34
5.1 Local Transformation . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2 Global Transformation . . . . . . . . . . . . . . . . . . . . . . . 35
6 Experimental Results of PLA CrosstalkMinimization . . . . . . . . . . 39
Crosstalk Minimization in Technology Mapping 47
1 Motivation of Crosstalk-aware Synthesis . . . . . . . . . . . . . . . . . 47
2 Relations of Wire Adjacency in Physical Level and I/O of Mapped Cell
in Synthesis Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.1 Wire Adjacency and I/O of Mapped Domino Cells . . . . . . . . 50
2.2 Crosstalk Immunity of OR Gates . . . . . . . . . . . . . . . . . 52
2.3 Cost Function for Crosstalk in TechnologyMapping . . . . . . . 54
3 Algorithm of Crosstalk Minimization in Technology Mapping . . . . . . 58
3.1 Flow of Crosstalk-aware Domino Circuit Synthesis . . . . . . . . 58
3.2 Output Phase Selection . . . . . . . . . . . . . . . . . . . . . . 60
iv
3.3 Parameterized TechnologyMapping . . . . . . . . . . . . . . . . 61
4 Experimental Results of Crosstalk-aware Synthesis . . . . . . . . . . . . 62
Crosstalk-aware Routing for Delay Optimization 71
1 Motivation of Crosstalk-aware Routing for Delay Optimization . . . . . 71
2 Design Flow of Crosstalk-aware and Performance-driven Routing . . . . 72
3 Performance-driven Routing . . . . . . . . . . . . . . . . . . . . . . . . 72
3.1 Wire Delay Estimation . . . . . . . . . . . . . . . . . . . . . . . 74
3.2 CriticalWire Routing . . . . . . . . . . . . . . . . . . . . . . . 75
3.3 Dynamic Delay Updating . . . . . . . . . . . . . . . . . . . . . 78
4 Crosstalk-avoidance Re-routing . . . . . . . . . . . . . . . . . . . . . . 78
5 Experimental Results of Crosstalk-aware and Performance-driven Routing 80
Conclusion and Future Work 85

                                

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