由於功率值高低對於電路的可靠度有相當的影響力，因此對於超大型積體電路來說，峰值功率估算成為重要的議題，這個議題主要關鍵在於怎樣的向量組會導致峰值功率，對於有上百個輸入的超大型積體電路而言，如果要搜尋所有可能的向量組，將會非常耗時且不實際，因此，在這篇論文中應用螞蟻演算法在峰值功率估算的議題上，而螞蟻演算法是仿效螞蟻在尋找食物的行為所提出來的演算法，接著我們會輸出高度可能發生峰值功率的向量組，並且考慮在 TSMC 0.18 um 和 TSMC 0.13 um 這兩種不同的製程下，將這些向量組輸入一個商業的功率計算工具 --- PrimePower，來幫助分析功率，最後的實驗結果顯示不論是對於組合電路或循序電路，都能有不錯的改善。

[1] T. Chou and K. Roy, \Accurate Power Estimation of CMOS Sequential Circuits,"
IEEE Trans. VLSI Systems, pp. 369-380, Sep. 1996.
[2] S. Chowdhury and J. S. Barkatullah, \Estimation of maximum current in MOS
IC logic circuits," IEEE. Trans. Computer-Aided Design, pp. 642_654, Jun.
1990.
[3] S. Devadas, K. Keutzer, and J. White, \Estimation of Power Dissipation
in CMOS Combinational Circuits Using Boolean Function Manipulation,"
IEEE. Trans. Computer-Aided Design, pp. 373-383, Mar. 1992.
[4] M. Dorigo and T. Stutzle, Ant Colony Optimization, Cambridge, MA: MIT
Press, 2004.
[5] A. Ghosh, S. Devadas, K. Keutzer, and J. White, \Estimation of Average
Switching Activity in Combinational and Sequential Circuits," in Proc. Design
Automation Conf., pp. 253-259, 1992.
[6] A. Krstic and K. T. Cheng, \Vector Generation for Maximum Instantaneous
Current Through Supply Lines for CMOS Circuits," in Proc. Design Automa-
tion Conf., pp. 383-388, 1997.
[7] M. S. Hsiao, E. M. Rudnick, and J. H. Patel, \E_ects of Delay Model in Peak
Power Estimation of VLSI Sequential Circuits," in Proc. Int. Conf. Computer-
Aided Design, pp. 45-51, 1997.
[8] M. S. Hsiao, E. M. Rudnick, and J. H. Patel, \K2: An Estimator for Peak
Sustainable Power of VLSI Circuits," in Proc. Int. Symp. Low Power Electronics
and Design, pp. 178-183, 1997.
[9] M. S. Hsiao, \Peak Power Estimation Using Genetic Spot Optimization for
Large VLSI Circuits," in Proc. Design, Automation, and Test in Europe, pp.
175-179, 1999.
[10] C. T. Hsieh, J. C. Lin, and S. C. Chang, \Vectorless Estimation of Maximum
Instantaneous Current for Sequential Circuits," IEEE. Trans. Computer-Aided
Design, pp. 2341-2352, Nov. 2006.
[11] S. Manne, A. Pardo, R. I. Bahar, G. D. Hachtel, F. Somenzi, E. Macii, and
M. Poncino, \Computing the Maximum Power Cycles of a Sequential Circuit,"
in Proc. Design Automation Conf., pp. 23-28, 1995.
[12] F. N. Najm, \A Survey of Power Estimation Techniques in VLSI Circuits,"
IEEE Trans. VLSI Systems, pp. 446-455, Dec. 1994.
[13] F. N. Najm, S. Goel and I. N. Hajj, \Power Estimation in Sequential Circuits,"
in Proc. Design Automation Conf., pp. 635-640, 1996.
[14] E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha,
H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, \SIS: A
System for Sequential Circuit Synthesis," Technical Report UCB/ERL M92/41,
Electronics Research Lab, Univ. of California, Berkeley, CA 94720, May 1992.
[15] C. Small, \Shrinking Devices Put the Squeeze on System Packaging," EDN.,
pp. 41-46, Feb. 1994.
[16] Synopsys Corporation. PrimePower Manual, May 2002.
[17] T. Uchino, F. Minami, T. Mitsuhashi, and N. Goto, \Switching Activity Analysis
Using Boolean Approximation Method," in Proc. Int. Conf. Computer-Aided
Design, pp. 20-25, 1995.
[18] H. J. M Veendrick, \Short-Circuit Dissipation of Static CMOS Circuitry and
Its Impact on the Design of Bu_er Circuits," IEEE J. Solid-State Circuits, vol.
SC-19, pp. 468-473, 1984.
[19] C. Wang, K. Roy, and T. Chou, \Maximum Power Estimation for Sequential
Circuits Using a Test Generation-based Technique," in Proc. Custom Integrated
Circuits Conf., pp. 229-232, 1996.