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研究生： 江振龍
Jhen-Long Jiang
論文名稱： 混合式FPGA架構之佈局及繞線演算法
Placement and Routing Algorithm for Mixed FPGA Architecture
指導教授： 黃婷婷
TingTing Hwang
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2004
畢業學年度： 92
語文別： 中文
論文頁數： 39
中文關鍵詞： 佈局 、繞線 、可程式規劃邏輯陣列
外文關鍵詞： placement, routing, FPGA
相關次數： 點閱：2  下載：0 
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    • 在[5]中，提出了一個新的混合式FPGA架構，此架構主要在改善先前所提出的層級式FPGA架構的繞線彈性，因此對此新架構而言，其包含電路延遲的可預估性及使繞線更具彈性的特性，在本文中將探討設計電路如何在此新FPGA架構上佈局及繞線的方法。並且，在實驗中將比較混合式FPGA架構及層級式FPGA架構架構之間的優劣。

    第一章 簡介 1 第二章 相關研究 7 第三章 新混合式FPGA架構 11 第一節 架構描述...................................11 第二節 架構參數化.................................16 第三節 設計流程...................................19 第四章 設計電路在層級式連接架構的佈局及繞線演算 21 第一節 圖形化層級式連接架構.......................21 第二節 接線的繞線優先權...........................24 第三節 佈局及繞線演算法...........................26 第五章 使用VPR實現設計電路在對稱式連接架構的佈局及繞線 30 第六章 實驗結果 32 第七章 總結 36 參考文獻 37

    [1] Taraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, and Majid Sarrafzadeh, “Innovate or Perish: FPGA Physical Design,” International Symposium on Physical Design, pp. 148-155, 2004.
    [2] Xilinx Inc., “The Programmable Logic Data Book”, 1994.
    [3] Yen-Tai Lai and Ping-Tsung Wang, “Hierarchical Interconnection Structures for Field Programmable Gate Arrays,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 5, pp. 186-196, June 1997.
    [4] P. T. Wang, K. N. Chen, and Y. T. Lai, “A High Performance FPGA with Hierarchical Interconnection Structure,” International Symposium on Circuits and Systems, pp. 4.239-4.242, 1994.
    [5] Chung-Yu Liu, “Architecture Evaluation of Hierarchical and Mixed FPGA Structure,” Thesis of National Tsing Hua University, 2004.
    [6] V. Betz and J. Rose, “VPR: A New Packing, Placement and Routing Tool for FPGA Research,” International Workshop on Field-Programmable Logic and Application, pp. 213-222, 1997.
    [7] Alexander, Marquardt, Vaughn Betz and Jonathan Rose, “Timing-Driven Placement for FPGAs,” International Symposium on Field Programmable Gate Arrays, pp.203-213, 2000.
    [8] Tim(Tianming) Kong, “A Novel Net Weighting Algorithm for Timing-Driven Placement,” International Conference on Computer Aided Design, pp. 172-179, 2002.
    [9] Jing-Jou Tang and Ping-Tsung Wang, ”A Efficient Placement and Global Routing Algorithm for Hierarchical FPGAs,” International Symposium on Circuits and Systems, pp. 4.729-4.732, 2000.
    [10] Michael Hutton, Khosrow Adibsamii and Andrew Leaver, ”Timing-Driven Placement for Hierarchical Programmable Logic Devices,” International Symposium on Field Programmable Gate Arrays, pp. 3-11, 2001.
    [11] S. Brown, J. Rose, and Z. G. Vranesic, “A Detailed Router for Field-programmable Gate Arrays,” IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems, Vol. 11, No. 5, pp. 620-628, May 1992.
    [12] F. D. Lewis andW. C.-C Pong, “A Negative Reinforcement Method for PGA Routing,” Annual ACM IEEE Design Automation Conference, pp. 601-605, 1993.
    [13] G. G. Lemieux and S. D. Brown, “A Detailed Routing Algorithm for Allocating Wire Segments in Field-programmable Gate Arrays,” ACM Physical Design Workshop, pp. 215-226, 1993.
    [14] M. J. Alexander and G. Robins, “New Performance-driven FPGA Routing Algorithms,” Annual ACM IEEE Design Automation Conference, pp. 562-567, 1995.
    [15] Y. Sun and C. L. Liu, “Routing in a New 2-dimensional FPGA/FPIC Routing Architecture,” Annual ACM IEEE Design Automation Conference, pp. 171-176, 1994.
    [16] Y. Sun, T.-C.Wang, C. K.Wang, and C. L. Liu, “Routing for Symmetric FPGAs and FPICs,” International Conference on Computer Aided Design, pp. 486-490, 1993.
    [17] Wei-Lun Hung, “Placement and Routing for Hierarchical FPGA,” Thesis of National Tsing Hua University, 2002.

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