當通道長度及氧化層厚度持續縮小,電晶體露電流會變的更嚴重,露電流的成分包含有次臨限電流,介面空乏區的表面/本體熱產生電流,閘極直接穿隧電流等等;而且,根據許多研究歸納指出當負閘極偏壓時之穿隧電流發生於閘極與汲極重疊的區域,稱此現象為"gate-induced drain leakage current (GIDL)”.根據SIA的計畫,通道長度為50-70 nm 的互補式電晶體,僅有1.5-2.0 nm閘氧化層厚度,相當於2-3 層原子厚度.在如此薄之閘氧化層下,閘極直接穿隧電流與閘極衍生之汲極露電流會變得更明顯,即使在低電壓下也會有很高的電場。
在GIDL中,於閘極與汲極重疊的區域之閘氧化層厚度與摻雜濃度扮演著很重要的角色,而且此露電流對氧化層厚度,汲極濃度,水平汲極濃度梯度很敏感,在閘極與汲極重疊的區域,因為閘汲功函數與高汲極濃度會加強電場強度,所以,最近抑制GIDL電流的方法使使用低摻雜濃度LDD元件抑制電場。

在本篇論文中，我們研究了可用於n型金氧半電晶體之氧化層厚度為20 Å, 26 Å 及 50 Å 的GIDL 模型。在高電場時，證明GIDL於閘極與深空乏汲極重疊區的產生為能帶穿隧機制。

我們驗證了已發表的GIDL模型並不適用於樣本數據。因為閘極與汲極重疊區的表面電場在GIDL模型中扮演極重要的角色，為了觀察表面電場，我們先使用tsuprem4 產生與樣本相似之結構，然後再使用Medici 模擬元件特性及閘極與汲極重疊區的表面電場。而且，我們推導出一個可適用於樣本數據的新模型。

As the channel length and the gate oxide thickness are scaled down, the off-state MOSFETs’ leakage current becomes more severe. The off-state leakage components are the sub-threshold current, surface/bulk thermal generation of carriers in the junction space-charge region, gate direct tunneling current etc. Furthermore, Many researchers have attributed the leakage current to the band-to-band tunneling occurring in the overlay region at negative gate bias and named the phenomenon “gate-induced drain leakage current (GIDL)”.According to the SIA roadmap, CMOS with gate length of 50-70 nm needs an oxide thickness of around 1.5-2.0 nm, which corresponds to 2-3 layers of atoms. With such a thin gate oxide, the gate direct tunneling current and the gate induced drain leakage current would become more apparent at low voltage due to the high electric field at low voltage.
The exact oxide thickness and doping profiles in the gate-to-drain overlay region play important roles in the GIDL current. And this leakage current is very sensitive to the oxide thickness, drain concentration, and lateral drain doping gradient. In the gate-to-drain overlay region, since the gate work function and high drain concentration would serve to enhance the field strength. So, recently complete suppression of the GIDL current has been demonstrated for low-concentration LDD devices by suppressing the electric field.

At somewhat higher field, the band-to-band tunneling in the gate-overlapped deep-depletion drain region has been proven to be the generation mechanism for Gate-Induced Drain Leakage (GIDL). In this thesis, we investigate GIDL models with n-MOSFETs oxide thickness of 20 Å, 26 Å, and 50 Å, respectively.

We show that the published GIDL models are not well fitting to our measured data. Since the surface electric field in the gate-to-drain overlay region play important roles in the GIDL current. In order to observe the surface electric field, we generate tsuprem4 structures whose aspects are similar to the measured samples. Then, devices characteristic are simulated with Medici to observe the surface electric field in the gate-overlapped-drain region. Moreover, we derive a new GIDL model and fitting well with measured data.

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