本篇論文主要為研製水平式閘極氮化鎵金氧半場效電晶體於藍寶石基板上，磊晶結構最上方為重摻雜之P型氮化鎵，其厚度分為50 nm及100 nm，黃光製程前先進行活化製程以利於基極歐姆接觸之製作，經過量測與計算，接觸電阻率分別為9.14×10-2及2.17×10-1 Ω-cm2。
本論文使用感應式耦合電漿蝕刻系統(ICP-RIE)進行氮化鎵蝕刻製程，但材料表面會因電漿蝕刻而受損，為了修復表面，本論文採用不同表面處理方式，分別為：(a) 浸泡鹽酸、BOE及硫酸等酸性溶液，(b) 以低瓦數之ICP-RIE進行化學性乾式蝕刻，(c) 以85 ℃之TMAH溶液浸泡一小時，以及(d) 在450 ℃環境下進行20次的Digital etch等方式互相搭配。
由量測結果可得，以Digital etch進行表面處理之試片擁有最佳的電性，其閾值電壓為4.21 V，最大汲極電流密度為3.61 mA/mm，計算後得到其場效遷移率為24.42 cm2/V-s。

In this study, GaN-based planar gate MOSFETs were fabricated on sapphire substrate. A heavily-doped P-type GaN layer was grown on the top of the epitaxial structure. The heavily-doped P-type GaN is with different thickness of 50 nm and 100 nm. The contact resistivity of body contact was 9.14×10-2 Ω-cm2 for 50 nm and 2.17×10-1 Ω-cm2 for 100 nm, respectively. In order to fabricate body ohmic-contact, the activation process was done before the lithography process.
The GaN-etching process was done by the inductively coupled plasma reactive ion etching system (ICP-RIE). It might cause damage to the surface of GaN because of the plasma etching process. In order to recover the surface quality, different methods of surface treatment were carried out and compared, namely: (a) soaking in hydrochloric acid, BOE and Sulfuric acid, (b) chemistry dry-etching by the low-power ICP-RIE, (c) soaking in TMAH solution at 85 ℃ for an hour, and (d) 20 cycles of digital etch at 450 ℃.
From the measurement, it was found that the best device performance was achieved with 20 cycles of digital etch at 450 ℃. With a threshold voltage of 4.21 V and a maximum drain current density of 3.61 mA/mm, the calculated field-effect mobility is 24.42 cm2/V-s.

[1] M. N. Yoder, “Wide bandgap semiconductor materials and devices,” IEEE Transactions on Electron Devices, vol. 43, no. 10, October 1996, pp. 1633-1636
[2] N. Kaminski, “State of the art and the future of wide band-gap devices,” IEEE Power Electronics and Applications, 13th European Conference, October 2009
[3] J. Millan, P. Godignon and X. Perpiñà, “A survey of wide bandgap power semiconductor devices,” IEEE Transactions on Power Electronics, vol. 29, no. 5, May 2014, pp. 2155-2163
[4] S. Dimitrijev, J. Han, D. Haasmann and H. Amini, “Power-switching applications beyond silicon: Status and future prospects of SiC and GaN devices,” IEEE Microelectronics Proceedings, 29th International Conference, June 2014, pp. 43-47
[5] S. Nakamura, T. Mukai, M.Senoh and N. Iwasa, “Thermal annealing effects on P-type Mg-doped GaN films,” Jpn. J. Appl. Phys., vol. 31, February 1992, pp. 139-142
[6] S. Nakamura, N. Iwasa and M. Senoh, “Method of manufacturing P-type compound semiconductor,” United States Patent, April 1994
[7] K. Matocha, T. P. Chow and R. J. Gutmann, “High-voltage normally off GaN MOSFETs on sapphire substrates,” IEEE Transactions on Electron Devices, vol. 52, no. 1, January 2005, pp. 6-10
[8] W. Huang, T. Khan and T. P. Chow, “Enhancement-mode n-channel GaN MOSFETs on P and N-GaN/sapphire substrates,” IEEE Electron Device Letters, vol. 27, no. 10, October 2006, pp. 796-798
[9] Y. Niiyama, T. Shinagawa, S. Ootomo, H. Kambayashi, T. Nomura and S. Yoshida, “High-quality SiO2/GaN interface for enhanced operation field-effect transistor,” phys. stat. sol., vol. 204, no. 6, June 2007, pp. 2032-2036
[10] Y. Niiyama, H. Kambayashi, S. Ootomo, T. Nomura and S. Yoshida “250 ℃ operation normally-off GaN MOSFETs,” Solid-State Electronics, vol. 51, no. 5, May 2007, pp. 784-787
[11] Y. Q. Wu, P. D. Ye, G.D. Wilk and B. Yang, “GaN metal-oxide-semiconductor field-effect-transistor with atomic layer deposited Al2O3 as gate dielectric,” Materials Science and Engineering B, Vol. 135, no. 3, December 2006, pp. 282-284
[12] Y. C. Chang, W. H. Chang, H. C. Chiu, L. T. Tung, C. H. Lee, K. H. Shiu, M. Hong, J. Kwo, J. M. Hong and C. C. Tsai, “Inversion-channel GaN metal-oxide-semiconductor field-effect transistor with atomic-layer-deposited Al2O3 as gate dielectric,” Applied Physics Letters, vol. 93, no. 5, August 2008
[13] W. B. Lanford, T. Tanaka, Y. Otoki and I. Adesida, “Recessed-gate enhancement-mode GaN HEMT with high threshold voltage,” IEEE Electronics Letters, vol. 41, no. 7, March 2005, pp. 449-450
[14] M. Kodama, M. Sugimoto1, E. Hayashi, N. Soejima, O. Ishiguro, M. Kanechika, K. Itoh, H. Ueda, T. Uesugi and T. Kachi, “GaN-based trench gate metal oxide semiconductor field-effect transistor fabricated with novel wet etching,” Applied Physics Express, vol. 1, no. 2, February 2008
[15] K. W. Kim, S. D. Jung, D. S. Kim, H. S. Kang, K. S. Im, J. J. Oh, J. B. Ha, J. K. Shin and J. H. Lee, “Effects of TMAH treatment on device performance of normally off Al2O3/GaN MOSFET,” IEEE Electron Device Letters, vol. 32, no. 10, October 2011, pp. 1376-1378
[16] D. Buttari, S. Heikman, S. Keller and U. K. Mishra, “Digital etching for highly reproducible low damage gate recessing on AlGaN/GaN HEMTs,” High Performance Devices, IEEE Lester Eastman Conference, August 2002
[17] Y. Wang, M. Wang, B. Xie, C. P. Wen, J. Wang, Y. Hao, W. Wu, K. J. Chen and B. Shen, “High-performance normally-off Al2O3/GaN MOSFET using a wet etching-based gate recess technique,” IEEE Electron Device Letters, vol. 34, no. 11, September 2013, pp. 1370-1372
[18] G. C. DeSalvo, C. A. Bozada, J. L. Ebel, D. C. Look and J. P. Barrette, “Wet chemical digital etching of GaAs at room temperature,” J. Electrochem. Soc., vol. 143, no. 11, April 1996, pp. 3652-3656
[19] X. Cao and I. Thayne, “Novel high uniformity highly reproducible non-selective wet digital gate recess etch process for InP HEMTs,” Microelectronic Engineering, vol. 67-68, June 2003, pp. 333-337
[20] A. Alian, C. Merckling, G. Brammertz, M. Meuris, M. Heyns and K. D. Meyer, “InGaAs MOS transistors fabricated through a digital-etch gate-recess process and the influence of forming gas anneal on their electrical behavior,” ECS Journal of Solid State Science and Technology, vol. 1, no. 6, October 2012, pp. 310-314
[21] V. Djara, K. Cherkaoui, T. Lopez, É. O’Connor, I. M. Povey, K. K. Thomas and P. K. Hurley, “Junctionless InGaAs MOSFETs with InAlAs barrier isolation and channel thinning by digital wet etching,” Device Research Conference (DRC), 71st Annual, June 2013
[22] J. Lin, X. Zhao, D. A. Antoniadis and J. A. del Alamo, “A novel digital etch technique for deeply scaled III-V MOSFETs,” IEEE Electron Device Letters, vol. 35, no. 4, April 2014, pp. 440-442
[23] X. Zhao and J. A. del Alamo, “Nanometer-scale vertical-sidewall reactive ion etching of InGaAs for 3-D III-V MOSFETs,” IEEE Electron Device Letters, vol. 35, no. 5, May 2014, pp. 521-523
[24] A. Vardi, X. Zhao and J. A. del Alamo, “InGaAs double-gate fin-sidewall MOSFET,” Device Research Conference (DRC), 72nd Annual, June 2014
[25] S. Lee, C. Y. Huang, A. D. Carter, J. J. M. Law, D. C. Elias, V. Chobpattana, B. J. Thibeault, W. Mitchell, S. Stemmer, A. C. Gossard and M. J. W. Rodwell, “High transconductance surface channel In0.53Ga0.47As MOSFETs using MBE source-drain regrowth and surface digital etching,” Indium Phosphide and Related Materials (IPRM), International Conference, May 2013
[26] S. D. Burnham, K. Boutros, P. Hashimoto, C. Butler, D. W. S. Wong, M. Hu and M. Micovic, “Gate-recessed normally-off GaN-on-Si HEMT using a new O2-BCl3 digital etching technique,” Phys. Status Solidi C, vol. 7, no. 7-8, July 2010, pp. 2010-2012
[27] Y. C. Liao, “Study on recessed MOS gate for GaN FETs,” Master’s Thesis, Institute of electronics engineering, National Tsing Hua University, June 2016
[28] I. H. Yu, “Investigation on characteristics of quasi-vertical trench gate GaN MOSFET treated with digital etch,” Master’s Thesis, Institute of electronics engineering, National Tsing Hua University, July 2017
[29] C. C. Kao, H. W. Huang, J. Y. Tsai, C. C. Yu, C. F. Lin, H. C. Kuo and S.C. Wang, “Study of dry etching for GaN and InGaN-based laser structure using inductively coupled plasma reactive ion etching,” Materials Science and Engineering, vol. 107, no. 3, March 2004, pp. 283-288
[30] M. S. P. Reddy, J. H. Lee and J. S. Jang, “Electrical characteristics of TMAH-surface treated Ni/Au/Al2O3/GaN MIS Schottky structures,” Electronic Materials Letters, vol. 10, no. 2, March 2014, pp. 411-416
[31] J. L. Autran, F. Seigneur, C. Plossu and B. Balland, “Characterization of Si-SiO2 interface states: Comparison between different charge pumping and capacitance techniques,” Journal of Applied Physics, vol. 74, no. 6, June 1993, pp. 3932-3935

[32] J. S. Brugler and P. G. A. Jespers, “Charge pumping in MOS devices,” IEEE Transactions on Electron Devices, vol. 16, no. 3, March 1969, pp. 297-302
[33] D. K. Schroder, “Semiconductor material and device characterization,” Third Edition, 2006, pp. 352-359
[34] J. L. Autran, B. Balland and G. Barbottinc, “Charge pumping techniques: Their use for diagnosis and interface states studies in MOS transistors,” Instabilities in Silicon Devices, 1999, pp. 405-493
[35] S. Jakschik, A. Avellan, U. Schroeder and J. W. Bartha, “Influence of Al2O3 dielectrics on the trap-depth profiles in mos devices investigated by the charge-pumping method,” IEEE Transactions on Electron Devices, vol. 51, no. 12, December 2004, pp. 2252-2255
[36] S. W. Yoo, “Analysis on characteristics and trapping mechanism of trap sites inside dielectric or drain causing random telegraph noise in trap-assisted tunneling GIDL,” Ph. D. Dissertation, Department of electrical and computer engineering college of engineering, Seoul national university, February 2016, pp. 49-57