本篇論文探討了通道結構與通道摻雜對於鰭式電晶體與奈米片電晶體之電性影響，對於先進電晶體，電晶體內通道與汲源極的結構是非常重要的，本篇論文的實驗證實了，利用現有的半導體製程技術與創意，即能進一步增進電晶體與薄膜電晶體(thin-film transistor)的特性。第一個討論的結構為垂直堆疊通道之多晶矽薄膜電晶體，實驗證明此結構可以有效降低連電阻，增加驅動電流，由於多晶矽/二氧化矽堆疊為標準半導體與面板製程，因此垂直堆疊之多晶矽通道是低成本且可實現之製程。本篇論文亦提出了閘極控制之抬升式汲源極結構(Gated raised S/D)，閘極控制之抬升式汲源極結構是將閘極氧化層延伸到汲源極，因此閘極不僅能控制通道亦可控制汲源極，在本篇論文的實驗中，具有閘極控制之抬升式源汲極已被證實能夠有效幫助降低奈米片(Nanosheet)無接面電晶體(Junctionless Transistor)內的短通道效應且降低汲源極之串聯電阻，基於閘極控制之抬升式汲源極的無接面電晶體特性，我們提出了電性接面(electrical junction)的觀念，我們利用電性接面解釋了，無接面電晶體的電性與傳統反轉式電晶體之電性為何如此相像，電性接面成因是因為通道與閘極的功函數差會使得通道內產生空乏層，導致在鰭式電晶體或奈米片無接面電晶體內，通道與汲源極產生載子濃度差，因此通道與汲源極交界處會產生累積電荷，形成電性接面，在關閉電晶體的狀態下，通道依然維持高電位，阻止無接面電晶體汲源極內的載子通過通道，令無接面電晶體有了開關特性，此外，更利用電性接面清楚解釋閘極控制之抬升式汲源極結構為何能夠降低無接面電晶體之短通道效應。電性接面的基本觀念亦可利用在傳統電晶體，利用閘極電壓控制奈米片通道之載子濃度，加上閘極電壓後的奈米片通道內，其等效載子濃度被升高，通道與汲極的濃度差加大，為了平衡濃度差，電晶體之汲極內的水平電場被提高了，此特性可利用於浮停閘記憶體的寫入機制，使用帶對帶穿隧誘發熱電子注入(band-to-band tunneling induced injection)的寫入機制下，寫入電子速度倍增，所需要的電壓大幅下降，因此奈米片非揮發性記憶體可以實現低電壓低耗電之操作。鍺被視為未來提高通道載子遷移率之重要材料，對於未來可能的鍺技術與平台，非揮發性記憶體是非常重要的電子元件，本篇論文中驗證了鍺通道雙電晶體(Ge Twin-transistor)之非揮發性記憶體，擁有高效能且高可靠度，雙電晶體之非揮發性記憶體是將電荷儲存在浮停閘內，浮停閘是利用連接兩個電晶體之閘極，利用此浮停閘儲存資料，因為不需要增加光罩與製程，對於未來先進鍺製程，鍺通道雙電晶體之非揮發性記憶體是適合使用於內嵌式記憶體之應用。

This dissertation includes the study the structure of the channel and the S/D in the FinFET/Nanosheet FET. The structure of the channel and the S/D is crucial for modern advanced CMOS technology above 16 nm technology node. Based on the experimental results of this dissertation, there are some novel methods to enhance the performance of FETs and thin-film transistors (TFTs), and these methods are based on the current Si manufacturing technology.
The Nanosheet FETs with stacked channels or gated raised S/D are studied in this dissertation. The stacked double-layer Nanosheet TFT is demonstrated and shows very low parasitic resistance. Moreover, the stacked double-layer Nanosheet TFT has low cost and is easy to fabricate. The Nanosheet junctionless transistor with the gated raised S/D is further discussed in this dissertation. The gated raised S/D can relieve the short-channel effect and reduce S/D parasitic resistance. The concept of electrical junction is proposed to illustrate why the transfer characteristics of the junctionless transistor are similar to that of the inversion-mode transistor. The work function difference between the gate and the channel creates depletion region in the channel in the junctionless transistor. And the carrier concentration changes due to this depletion region in the ultra-thin channel. The carrier concentration difference between the channel and the S/D builds the electrical junction in the junctionless transistor. The electrical junction can also be used to explain how the gated raised S/D helps to relieve the short-channel effect. Moreover, the electrical junction inspires our group to invent a low voltage programmable inversion-mode Nanosheet TFT nonvolatile memory using BBHE programming method. The BBHE method requires high source-to-drain electric field. The Nanosheet structure enhances the source-to-drain electric field in the BBHE operation. Thus, the p-type inversion-mode Nanosheet TFT nonvolatile memory suits for low-voltage/low-power memory applications. Finally, a Ge-channel Twin-transistor FinFET nonvolatile memory is demonstrated and shows satisfactory performance and reliability. The charges are stored in the connected gate of the two transistors. Therefore, no additional mask or manufacturing process is required for the Ge-channel Twin-transistor nonvolatile memory. The investigation examines the feasibility of Ge-channel embedded Twin-TFT nonvolatile memory on the future Ge-based technology.

References of Chapter 1
1-1. T. Skotnicki, “Heading for Decananometer CMOS-Is Navigation Among Icebergs Still a Viable Strategy?” Proc. of the 30th European Solid- State Device Research Conference, Gif-Sur-Yvette, France, 2000, pp. 19 - 33.
1-2. Bi. Y. Nguyen, C. Mazuré, D. Delprat, C. Aulnette, N. Daval, F. Andr, and O. Faynot, “Overview of FDSOI technology from substrate to device,” International Semiconductor Device Research Symposium., pp. 1-2, 2009.
1-3. M. Jurczak, N. Collaert, A. Veloso, T. Hoffmann, and S. Biesemans, “Review of FINFET technology,” IEEE International SOI Conference, pp. 1-4, 2009.
1-4. Min-hwa Chi, “FinFET technology: Overview and status at 14nm node and beyond,” China Semiconductor Technology International Conference (CSTIC), pp.1-3, 2016.
1-5. N. Louber, T. Hook, P. Montanini, C. W. Yeung, S. Kanakasabapathy, M. Guillom, T. Yamashita, J. Zhang, X. Miao, J. Wang, A. Young, R. Chao, M. Kkang, Z. Liu, S. Fan, B. Hamieh, S. Sieg Y. Mignot, W. Xu, S.-C. Seo, J. Yoo, S. Mochizuki, M. Sankarapandian, O. Kwon, A. Carr, A. Greene, Y. Park, J. Frougier, R. Galatage, R. Bao, J. Shearer, R. Conti, H. Song, D. Lee, D. Kong, Y. Xu, A. Arceo, Z. Bi, P. Xu, R. Muthinti, J. Li, D. Brown, P. Oldiges, R. Robison, J. Amold, N. Felix, S. Skordas, J. Gaudiello, T. Standaert, H. Jagannathan, D. Corliss, M.-H. Na, A Knorr, T. Wu, D. Gupta, S. Lian, R. Divakaruni, T. Gow, C. Labelle, S. Lee, V. Paruchuri, H. Bu, and M. Khare, "Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET," in VLSI Tech. Dig., 2017, pp. T230 - T231.
1-6. J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R.d Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
1-7. J. P. Colinge, C. W. Lee, N. Dehdashti Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, and R. Yu, “Junctionless Transistors Physics and Properties,” Semiconductor-On-Insulator Materials for Nanoelectronics Applications, pp.187-200, 2011.
1-8. S. J. Choi, D. I. Moon, S. Kim, J. P. Duarte, and Y. K. Choi, “Sensitivity of Threshold Voltage to Nanowire Width,” IEEE Electron Device Letters, vol. 32 , no. 2 , 2011.
1-9. C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, “Junctionless multigate field-effect transistor,” Appl. Phys. Lett., vol. 94, no. 5, pp. 053511 2009.
1-10. R. Rios, A. Cappellani, M. Armstrong, A. Budrevich, H. Gomez, R. Pai, N. Rahhal-orabi, and K. Kuhn, “Comparison of Junctionless and Conventional Trigate Transistors With Lg Down to 26 nm,” IEEE Electron Device Letters, vol. 32 , no. 9 , pp. 1170 - 1172, 2011.
1-11. C. W. Lee, I. Ferain, N. D. Akhavan, P. Razavi, R. Yan, R. Yu, B. O'Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, S. Gheorghe, R. Murphy, J. P. Colinge, "Short-channel junctionless nanowire transistors", Proc. SSDM, pp. 1044-1045, 2010.
1-12. R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to Flash Memory,” Proc. IEEE 91, pp.489-502, 2003
1-13. D. Kahng, and S. M. Sze , “A floating gate and its application to memory devices,” Bell syst. Tech. J., vol. 46, no. 6, pp.1288-1295, 1967.
1-14. M. Lenzlinger and E. H. Snow, “Fowler-Mordheim Tunneling in thermal grown SiO2,” Appl. Phys. Lett. vol. 40, no. 1, pp. 278-284, 1969.
1-15. P. E. Cottrell, R. R. Troutma, and T. H. Ning, “Hot-electron emission in n-channel IGFETs,” IEEE J. Solid-state Circuits, vol. 14, pp. 442, 1979.
1-16. I. C. Chen, C. Kaya, and J. Paterson, “Band-to-band tunneling induced substrate hot-electron (BBISHE) Injection: A new programming mechanism for nonvolatile memory devices,” IEDM tech. Dig., pp. 263, 1989.
1-17. K. T. San, C. Kaya, and T. P. Ma, “Effects of Erase Source Bias On Flash EPROM Device Reliablity,” Transactions on Electron Devices, vol. 42, no. 1, pp. 150-159, 1995.
1-18. T. Ohnakado, H. Onoda, O. Sakamoto, K. Hayashi, N. Nishioka, H. Takada, K. Sugahara, N. Ajika, and S. Satoh, "Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron(BBHE) for Flash Memory with a P-channel Cell", in IEDM Tech. Dig., 1995, pp. 11.5.1 - 11.5.4.
1-19. P. Cappelletti, et al., “Failure mechanisms of Flash cell in program/erase cycling,” IEDM tech. Dig. pp. 291-294, 1994.
1-20. R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to Flash Memory,” Proc. IEEE 91, pp.489-502, 2003.
1-21. D. Esseni, L. Selmi, R. Bez, L. Ravazzi, and E. Sangiorgi, “Soft-programming in scaled EEPROM Flash memory cells,” Proc. ESSDERC 95, pp. 549-552, 1995.
1-22. Ki-Tae Park, Dae-Seok Byeon, and Doo-Hyun Kim, “A world's first product of three-dimensional vertical NAND Flash memory and beyond, ” in NVMTS, pp.1-5, 2014.

Reference of Chapter 2
2-1. S. Natarajan, M. Agostinelli, S. Akbar, M. Bost, A. Bowonder, V. Chikarmane, S. Chouksey, A. Dasgupta, K. Fischer, Q. Fu, T. Ghani, M. Giles, S. Govindaraju, R. Grover, W. Han, D. Hanken, E. Haralson, M. Haran, M. Heckscher, R. Heussner, P. Jain, R. James, R. Jhaveri, I. Jin, H. Kam, E. Karl, C. Kenyon, M. Liu, Y. Luo, R. Mehandru, S. Morarka, L. Neiberg, P. Packan, A. Paliwal, C. Parker, P. Patel, R. Patel, C. Pelto, L. Pipes, P. Plekhanov, M. Prince, S. Rajamani, J. Sandford, B. Sell, S. Sivakumar, P. Smith, B. Song, K. Tone, T. Troeger, J. Wiedemer, M. Yang, K. Zhang, and IEEE, "A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 mu m(2) SRAM cell size," 2014 IEEE International Electron Devices Meeting (IEDM), 2014.
2-2. B. H. Lee, J. Hur, M. H. Kang, T. Bang, D. C. Ahn, D. Lee, K. H. Kim, and Y. K. Choi, "A vertically integrated junctionless nanowire transistor," Nano Letters, vol. 16, pp. 1840-1847, Mar 2016.
2-3. H. B. Chen, Y. C. Wu, C. Y. Chang, M. H. Han, N. H. Lu, and Y. C. Cheng, "Performance of GAA poly-Si nanosheet (2nm) channel of junctionless transistors with ideal subthreshold slope," in 2013 Symposium on VLSI Technology, 2013, pp. T232-T233.
2-4. M. S. Yeh, Y. C. Wu, M. H. Wu, Y. R. Jhan, M. H. Chung, and M. F. Hung, "High performance ultra-thin body (2.4nm) poly-Si junctionless thin film transistors with a trench structure," in 2014 IEEE International Electron Devices Meeting, 2014, pp. 26.6.1-26.6.4.
2-5. Y. C. Cheng, H. B. Chen, C. S. Shao, J. J. Su, Y. C. Wu, C. Y. Chang, and T. C. Chang, "Performance enhancement of a novel P-type junctionless transistor using a hybrid poly-Si fin channel," in 2014 IEEE International Electron Devices Meeting, 2014, pp. 26.7.1-26.7.4.
2-6. R. J. Lyu, H. C. Lin, M. H. Wu, B. S. Shie, H. T. Hung, and T. Y. Huang, "Film profile engineering (FPE): A new concept for manufacturing of short-channel metal oxide TFTs," in 2013 IEEE International Electron Devices Meeting, 2013, pp. 11.2.1-11.2.4.
2-7. T. Naito, T. Ishida, T. Onoduka, M. Nishigoori, T. Nakayama, Y. Ueno, Y. Ishimoto, A. Suzuki, W. Chung, R. Madurawe, S. Wu, S. Ikeda, and H. Oyamatsu, "World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS," in 2010 Symposium on VLSI Technology, pp. 219-220, 2010.
2-8. R. Ishihara, J. Derakhshandeh, M. R. Tajari Mofrad, T. Chen, N. Golshani, and C. I. M. Beenakker, "Monolithic 3D-ICs with single grain Si thin film transistors," Solid-State Electronics, vol. 71, pp. 80-87, 2012.
2-9. F. Carta, S. M. Gates, A. B. Limanov, J. S. Im, D. C. Edelstein, and I. Kymissis, "Sequential lateral solidification of silicon thin films on Cu BEOL-integrated wafers for monolithic 3-D integration," IEEE Transactions on Electron Devices, vol. 62, pp. 3887-3891, 2015.
2-10. K. Ota, T. Irisawa, K. Sakuma, C. Tanaka, K. Ikeda, T. Tezuka, D. Matsushita, and M. Saitoh, "Silicon-compatible low resistance S/D technologies for high-performance top-gate self-aligned InGaZnO TFTs with UTBB (ultra-thin body and BOX) structures," in 2015 Symposium on VLSI Technology (VLSI Technology), pp. T214–T215, 2015.
2-11. Sentaurus TCAD Ver. 2014, Synopsys, Mountain View, CA, USA, 2014.
2-12. ITRS Roadmap 2015 [Online]. Available: http://www.semiconductors.org/main/2015_international_technology_roadmap_for_semiconductors_itrs/
2-13. C.E.D. Chen, M. Matloubian, R. Sundaresan, B.Y. Mao, C.C. Wei, And G.P. Pollack, “Single Transistor Latch In SOI MOSFETs,” IEEE Electron Device Lett., vol. 9, pp. 636-638, 1988. 

Reference of Chapter 3
3-1. J. P. Colinge, C. W. Lee, A. Afzaliant, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nature Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
3-2. C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, “Junctionless multigate field-effect transistor,” Appl. Phys. Lett., vol. 94, pp. 053511-1–053511-2, Feb. 2009.
3-3. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Y. Yang, C. Tabery, C. Ho, Q. Xiang, T. J. King, J. Bokor, C. Hu, M. R. Lin, and D. Kyser, “FinFET scaling to 10 nm gate length,” in IEDM Tech. Dig., 2002, pp. 251–254.
3-4. T. C. Liao, S. W. Tu, M. H. Yu, W. K. Lin, C. C. Liu, K. J. Chang, Y. H. Tai, and H. C. Ceng, “Novel gate-all-around poly-Si TFTs with multiple nanowire channels,” IEEE Electron Device Lett., vol. 29, no. 8,pp. 889–891, Aug. 2008.
3-5. C. J. Su, T. I. Tsai, Y. L. Liou, Z. M. Lin, H. C. Lin, and T. S. Chao, “Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels,” IEEE Electron Device Lett., vol. 32, no. 4, pp. 521 - 523, Apr. 2011.
3-6. N. Singh, K. D. Buddharaju, S. K. Manhas, A. Agarwal, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, and D.L. Kwong, “Si, SiGe nanowire devices by top-down technology and their applications,” IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3107–3118, Nov. 2008.
3-7. E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, “Theory of the Junctionless Nanowire FET,”IEEE Trans. Electron Devices, vol. 58, no. 9, pp. 2903 - 2910, Aug. 2005.
3-8. S. J. Choi, D. I. Moon, S. Kim, J. P. Duarte, and Y. K. Choi, “Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors,” IEEE Electron Device Lett., vol. 32, no. 2, pp. 125 - 127, Feb. 2011.
3-9. H. B. Chen, Y. C. Wu, C. Y. Chang, M. H. Han, N. H. Lu, and Y. C. Cheng, “Performance of GAA poly-Si nano sheet (2nm) channel of junctionless transistors with ideal subthreshold slope,” VLSI Technol. Circuits, 2013, pp. T232-T233.
3-10. H. C. Lin, C. I. Lin, and T. Y. Huang, “Characteristics of n-type junctionless poly-Si thin-film transistors with an ultrathin channel,” IEEE Electron Device Lett., vol. 33, no. 1, pp. 53 - 55, Jan. 2012.
3-11. S. Migita, Y. Morita, T. Matsukawa, M. Masahara, and H. Ota, “Experimental Demonstration of Ultrashort-Channel (3nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI,” IEEE Trans. Electron Devices, vol. 13, no. 2, pp.208 -215, Mar. 2014.
3-12. A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M Jurczak, and D. Meyer “ Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs,” IEEE Trans. Electron Devices, vol. 52, no. 6, pp.1132 -1140, Jun. 2005
3-13. R. T. Doria, R. D. Trevisoli, and A. Pavanello, “Impact of the Series Resistance in the I-V Characteristics of nMOS Junctionless Nanowire Transistors,” ECS Trans., vol. 39, issue 1, pp. 231-238, 2011
3-14. M. S. Yeh, Y. C. Wu, M. H. Wu, Y. R. Jhan, M. H. Chung, and M. F. Hung, "High performance ultra-thin body (2.4 nm) poly-Si junctionless thin film transistors with a trench structure," in IEDM Tech. Dig., 2014, pp. 26.6.1 - 26.6.4.
3-15. C. W. Lee, A. Borne, I. Ferain, A. Afzalizn, R. Yan, N. D. Akhavan, P. Razavi, and J. P. Colinge,” High-temperature Performance of Silicon Junctionless MOSFETs,” IEEE Trans. Electron Devices, vol. 57, no. 3, pp.620 -625, Mar. 2010
 
Reference of Chapter 4
4-1. B. S. Doyle, S. Datta, M. Doczy, S Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, IEEE Electron Devices Lett., vol. 24, no. 4, pp.263-265, Apr. 2003.
4-2. C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks*, D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S. Joshi, C. Kenyon, H. Liu, R. McFadden, B. McIntyre, J. Neirynck, C. Parker, L. Pipes, I. Post, S. Pradhan, M. Prince, S. Ramey, T. Reynolds, J. Roesler, J. Sandford, J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki, K. Mistry, " A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors," in VLSI Tech. Dig., 2012, pp. 131 - 132.
4-3. Y. C. Wu, C. Y. Chang, T. C. Chang, P. T. Liu, C. S. Chen, C. H. Tu, H. -W. Zan, Y. H. Tai, and S. M. Sze, " High Performance and High Reliability Polysilicon Thin-Film Transistors with Multiple Nano-Wire Channels," in IEDM Tech. Dig., 2004, pp. 777 - 780.
4-4. R. T. Doria, R. D. Trevisoli, and A. Pavanello, "Impact of the Series Resistance in the I-V Characteristics of nMOS Junctionless Nanowire Transistors," ECS Trans., vol. 39, issue 1, pp. 231-238, 2011
4-5. J. P. Colinge, C. W. Lee, A. Afzaliant, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junctions," Nature Nanotechnol., vol. 5, no. 3, pp. 225-229, Mar. 2010.
4-6. C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, "Junctionless multigate field-effect transistor," Appl. Phys. Lett., vol. 94, pp. 053511-1-053511-2, Feb. 2009.
4-7. Y. C. Cheng, Y. C. Wu, H. B. Chen, M. H. Han, N. H. Lu, J. J. Su, and C. Y. Chang, “Junctionless multigate field-effect transistor," Appl. Phys. Lett., vol. 94, pp. 053511-1-053511-2, Feb. 2009.
4-8. M. S. Yeh, Y. C. Wu, M. H. Wu, Y. R. Jhan, M. H. Chung, and M. F. Hung, "High performance ultra-thin body (2.4 nm) poly-Si junctionless thin film transistors with a trench structure," in IEDM Tech. Dig., 2014, pp. 26.6.1 - 26.6.4.
4-9. L. C. Chen, M. S. Yeh, K. W. Lin, M. H. Wu, and Y. C. Wu, "Junctionless Poly-Si Nanowire FET With Gated Raised S/D," IEEE J-EDS, vol. 4, no. 2, Mar. 2016.
4-10. S. Migita, Y. Morita, T. Matsukawa, M. Masahara, and H. Ota, "Experimental Demonstration of Ultrashort-Channel (3 nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI," IEEE Trans. Electron Devices, vol. 13, no. 2, pp.208 -215, Mar. 2014.

Reference of Chapter 5
5-1. B. S. Doyle, S. Datta, M. Doczy, S Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, "High performance fully-depleted tri-gate CMOS transistors," IEEE Electron Devices Lett., vol. 24, no. 4, pp.263-265, Apr. 2003.
5-2. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Y. Yang, C. Tabery, C. Ho, Q. Xiang, T. J. King, J. Bokor, C. Hu, M. R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., 2002, pp. 251-254.
5-3. T. C. Liao, S. W. Tu, M. H. Yu, W. K. Lin, C. C. Liu, K. J. Chang, Y. H. Tai, and H. C. Ceng, “Novel gate-all-around poly-Si TFTs with multiple nanowire channels,” IEEE Electron Device Lett., vol. 29, no. 8,pp. 889–891, Aug. 2008.
5-4. N. Louber, T. Hook, P. Montanini, C. W. Yeung, S. Kanakasabapathy, M. Guillom, T. Yamashita, J. Zhang, X. Miao, J. Wang, A. Young, R. Chao, M. Kkang, Z. Liu, S. Fan, B. Hamieh, S. Sieg Y. Mignot, W. Xu, S.-C. Seo, J. Yoo, S. Mochizuki, M. Sankarapandian, O. Kwon, A. Carr, A. Greene, Y. Park, J. Frougier, R. Galatage, R. Bao, J. Shearer, R. Conti, H. Song, D. Lee, D. Kong, Y. Xu, A. Arceo, Z. Bi, P. Xu, R. Muthinti, J. Li, D. Brown, P. Oldiges, R. Robison, J. Amold, N. Felix, S. Skordas, J. Gaudiello, T. Standaert, H. Jagannathan, D. Corliss, M.-H. Na, A Knorr, T. Wu, D. Gupta, S. Lian, R. Divakaruni, T. Gow, C. Labelle, S. Lee, V. Paruchuri, H. Bu, and M. Khare, "Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET," in VLSI Tech. Dig., 2017, pp. T230 – T231.
5-5. T. M. Lee, M. H. Na, A Chu, A. Young, T. Hook, L. Liebmann, E. J. Nowak, S. H. Baek, R. Sengupta, H. Trombley, and X. Miao, "Accurate Performance Evaluation for the Horizontal Nanosheet Standard-Cell Design Space Beyond 7nm Technology," in IEDM Tech. Dig., 2017, pp. 29.3.1-29.3.4.
5-6. B. Jiankang, “On the go with SONOS,” IEEE Circuits Devices Mag., vol. 16, no. 4, pp. 22–31, Jan. 2000.
5-7. K. T. Park, D. S. Byeon and D. H. Kim, “A World’s First Product of Three-Dimensional Vertical NAND Flash Memory and Beyond,” in NVMTS, 2014, pp. 27-29.
5-8. T. Ohnakado, H. Onoda, O. Sakamoto, K. Hayashi, N. Nishioka, H. Takada, K. Sugahara, N. Ajika, and S. Satoh, “Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron(BBHE) for Flash Memory with a P-channel Cell”, in IEDM Tech. Dig., 1995, pp. 11.5.1 - 11.5.4.
5-9. M. T. Wu, H. T. Lue, K. Y. Hsieh, R. Liu, and C. Y. Lu, “Study of the Band-to-Band Tunneling Hot-Electron (BBHE) Programming Characteristics of p-Channel Bandgap-Engineered SNONS (BE-SONOS),” IEEE Trans. Electron Devices, vol. 54, no. 4, pp. 699–706, Apr. 2007.
5-10. Y. Sun, H. Y. Yu, N. Singh, K. C. Leong, E. Quek, G. Q. Lo, D. L. Kwong, “Demonstration of Memory String with Stacked Junction-Less SONOS Realized on Vertical Silicon Nanowire”, in IEDM Tech. Dig., 2011, pp. 223 - 226.
5-11. S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, P. S. Lin, B. H. Tseng, J. H. Shy, S. M. Sze, C. Y. Chang, and C. H. Lien,” A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory,” Applied Physical Letter, vol. 28 , no 9 , pp.809, Sep. 2007.
5-12. L. C. Chen, M. S. Yeh, Y. R. Lin, K. W. Lin, M. H. Wu, V. Thirunavukkarasu, and Y. C. Wu, “ The Physical Analysis on Electrical Junction of Junctionless FET,” AIP Advances, vol. 7, no 2, pp. 025301, Jan. 2017.
5-13. D. J. Griffiths, “Introduction to Quantum Mechanics, ” in Prentice–Hall, 2nd ed., ch. 2, Upper Saddle River NJ, 1995, pp.78-82.
5-14. Y Yang and et al., “Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures, ” Solid State Electronics, vol 44, 2000, pp 949-958.
5-15. C. C. Chao, and M. H. White, “Characterization of Charge Injection And Trapping in Scaled SONOS/MONS Memory Devices, ” Solid-State Electronics, vol 30, no 3, 1987, pp 307-319.

Reference of Chapter 6
6-1. B. S. Doyle, S. Datta, M. Doczy, S Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, "High performance fully-depleted tri-gate CMOS transistors," IEEE Electron Devices Lett., vol. 24, no. 4, pp.263-265, Apr. 2003.
6-2. C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks*, D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S. Joshi, C. Kenyon, H. Liu, R. McFadden, B. McIntyre, J. Neirynck, C. Parker, L. Pipes, I. Post, S. Pradhan, M. Prince, S. Ramey, T. Reynolds, J. Roesler, J. Sandford, J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki, K. Mistry, " A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors," in VLSI Tech. Dig., 2012, pp. 131 - 132.
6-3. Y. C. Wu, C. Y. Chang, T. C. Chang, P. T. Liu, C. S. Chen, C. H. Tu, H. W. Zan, Y. H. Tai, and S. M. Sze, " High Performance and High Reliability Polysilicon Thin-Film Transistors with Multiple Nano-Wire Channels," in IEDM Tech. Dig., 2004, pp. 777 - 780.
6-4. J. Feng, R. Woo, S. Chen, Y. Liu, P. B. Griffin, and J. D. Plummer, P-channel germanium FinFET based on rapid melt growth,” IEEE Electron Device Lett., vol. 28, no. 7, pp. 637–639, Jul. 2007.
6-5. Bin Liu, Xiao Gong, Genquan Han, Phyllis Shi Ya Lim, Yi Tong, Qian Zhou, Yue Yang, Nicolas Daval, Christelle Veytizou, Daniel Delprat, Bich-Yen Nguyen, and Yee-Chia Yeo, “High-Performance Germanium Ω-Gate MuGFETWith Schottky-Barrier Nickel Germanide,” IEEE Electron Device Lett., vol. 33, no. 10, pp. 1336–1338, Oct. 2012.
6-6. M.-S. Yeh, G.-L. Luo, F.-J. Hou, P.-J. Sung, C.-J. Wang, C.-J. Su, C.-T. Wu, Y.-C. Huang,T.-C. Hong, T.-S. Chao, B.-Y. Chen, K.-M. Chen, Y.-C. Wu, M. Izawa, M. Miura, M. Morimoto, H. Ishimura, Y.-J. Lee, W.-F. Wu, W.-K. Yeh, “Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by UsingIn-SituALD Digital O3Treatment,” IEEE J-EDS., vol. 6, pp. 1227 - 1232, Nov. 2018.
6-7. N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French, “The fabrication and characterization of EEPROM arrays on glass usinga low-temperature poly-Si TFT process,” IEEE Trans. Electron Devices,vol. 43, no. 11, pp. 1930–1936, Nov. 1996.
6-8. J. W. Lee, N. I. Lee, H. J. Chung, and C. H. Han, “Improved stability of polysilicon thin-film transistors under self-heating and high endurance EEPROMcells for systems-on-panel,” in IEDM Tech. Dig., 1998, pp. 265–268.
6-9. Y. C. Wu and et al, “Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure,” IEEE Electron Device Lett., vol. 29, no. 11, pp. 1226–1228, Oct. 2008.
6-10. M. K. Hudait, “Structural and band alignment properties of Al2O3 on epitaxial Ge grown on (100), (110), and (111)A GaAs substrates by molecular beam epitaxy,” Journal of Applied Physics, vol. 113, no. 13, pp.134311, Apr. 2013