本論文探討具有ONO間隙壁結構之0.25微米製程金氧半電晶體其熱載子效應特性。間隙壁緩衝氧化層厚度對於熱載子可靠度有顯著之影響力，我們發現多段式的熱載子衰退特性僅發生在加速老化條件為最大基底電流 (Vg Vd /2) 下，且使用較薄的緩衝氧化層NOLDD元件(100 Å)時。當測試元件之加速老化條件為最大基底電流 (Isubmax condition, Vg Vd /2)，在第一階段衰退(1ms~100s)呈現類似在高閘極電壓加速老化條件下(High-Vg-stressing-condition-like)的衰退特性，在此測試條件下產生之ONO間隙壁內補陷熱電子效應將不可再被忽略，且為第一階段元件衰退的主因。在第二階段 (100s之後)，其衰退特性與第一階段相較下呈現出較迅速的斜率，這是由於界面狀態 (interface states) 的產生。這現象指出，當元件間隙壁下之緩衝氧化層較薄時，熱電子補陷機制首先主宰元件第一階段的衰退，而後界面狀態開始產生且將與補陷熱電子機制相互競爭來主導元件第二階段的衰退。採用固定基底電流加速老化的實驗證實了靠近汲極端，其吸引熱電洞的垂直電場是產生界面狀態的主要原因。另外，具有不同緩衝氧化層厚度元件 (100 Å、150 Å) 的生命期 (Life-time) 也被評估之。
當熱電子被捕陷在ONO間隙壁內，用最大轉導外插法 (gm-maximum extrapolation technique) 之萃取數值用來分析元件的臨限電壓Vt衰退特性被證實為一不恰當的方式。大量的間隙壁熱電子補陷將導致汲極串聯電阻增加，這將使得元件轉導降低以及峰值轉導所對應的閘極電壓減小，此時最大轉導外插法所萃取之臨限電壓將變得更小且可能被誤判為電洞補陷效應。我們考慮串聯電阻效應對於最大轉導外插法所造成的影響來探討外插閘極電壓Vgsi 與汲極串聯電阻增量 的關係，最後推導出一個粹取的演算法並證明真正的元件臨限電壓在第一階段的熱載子加速老化過程中將維持不變

The hot carrier degradation of 0.25µm process LDD n-MOSFETs with nitride spacer and sidewall buffer oxide (NOLDD) is characterized in detail. We find that the sidewall buffer oxide thickness intensely affects hot carrier reliability. A mechanism of multi-stage hot carrier degradation (linear gm degradation) is observed and only occurs in NOLDD device with thinner sidewall buffer oxide (100Å) under maximum substrate current Isubmax stressing condition, (Vg Vd /2). In the early stage (1ms~100s), the device degradation for Isubmax stressing condition performs “high-Vg-stressing-condition-like” (Vg=Vd) characteristic due to nitride spacer trapped electrons, which cannot be ignored any more and is mostly responsible for device degradation. After 100s, the second stage degradation performs more rapid power law gradient due to interface states generation compared with early stage. It implies that the electrons trapping mechanism predominates the early stage degradation, and then interface states generation competes against electrons trapping mechanism to dominate the second stage gm degradation while the sidewall buffer oxide is thinner. An examination of constant substrate current stressing suggests that the vertical electric field attracting hot hole near the drain edge is the main cause of interface states generation. Lifetime evaluation for devices with different buffer oxide thickness of 100Å and 150 Å is also carried out for comparison.
While electrons are trapped in nitride spacer, the threshold voltage Vt extraction using gm-maximum exploration method in early stage hot carrier stress is proved to be an un-proper method to characterize device. Once a large amount of electrons trapped in nitride spacer, the drain series resistance increases, which transforms to reduce both transconductance gm and the corresponding gate-to-source voltage Vgs at which peak gm occurs. The threshold voltage Vt extracted with gm-maximum extrapolation method under this circumstance will become smaller and might be misjudged as trapped hole during the period of hot carrier stress. We consider the effect of series resistance on gm-maximum extrapolation method to find a relationship between the increased drain resistance and the decreased intercept gate voltage Vgsi. An extraction algorithm is derived, which establishes that the true threshold voltage of device remains unchanged under test during the early stage hot carrier stress.

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