隨著超大型積體電路(VLSI)製造技術的進步，系統單晶片(System-on-Chip)已成為積體電路設計的趨勢。系統單晶片將各種不同特性，不同型態的電路整合在同一塊晶片上，可以達到高效能，低功率損耗的需求。此外，晶片的操作頻率也越來越快，造成時間方面的缺陷越來越重要．在這篇論文中，我們提出一個針對系統單晶片中的微處理器(Microprocessor)，做功能性路徑延遲錯誤自我測試的方法。然而我們針對處理器找出功能性限制，並且利用功能性限制(Functional constraints)和自動測試樣本產生器(Automatic test patterns generation)去產生測試樣本，再將測試樣本轉為測試程式．測試程式由原來處理器的指令集所組成，並且利用指令集形式合成測試程式可以達到即時測試(At-Speed Testing)流程的需求。
測試程式的流程主要分成四個部份。第一部份，自動切割電路，將暫存器到暫存器之間的組合電路切割出來．第二部分，自動擷取功能性限制，利用硬體語言解譯器去擷取功能性限制．第三部分，自動測試樣本產生器。第四部份，自動回尋測試樣本，利用商業自動測試樣本產生器去回尋測試樣本，轉為測試程式，將測試程式放到指令記憶體達到自我測試的目的，我們可以由資料記憶體上的結果判斷微處理器的功能是否正常。整個測試程式的流程可以用來產生路徑延遲錯誤的測試程式。最後，本論文以一個Parwan微處理器進行測試程式合成的流程驗證。

In this paper, a functional path delay fault test flow is proposed for automatically extracting the constraints and generating the functional test patterns for processors and could be extended to ASICs. The Self-testing of an embedded processor core in a system-on-a-chip (SOC) by using its own instruction sequences has several potential benefits which include natural application of functional vectors at-speed, low DFT overhead, and better power and thermal management during testing. The functional constraints are generated by processor architecture and instruction set, and these constraints are applied to generate functional test patterns stage by stage. Then, a test program is synthesized by test patterns and processor architecture. Note that each step in the proposed functional test flow is automatic without manual operation. The Parwan processor is applied to demonstrate the test flow.

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