隨著製程演進至奈米時代，漏電流已成為不可忽略的問題，此外，靜態隨機存取記憶體的漏電流功率占了不少整合型系統晶片的功率耗，降低電源差對減少漏電流是十分有效的，在深次微米製程下，使用鉗地架構使得地電源線抬升對降低次臨界漏電流和閘極漏電流是常用的技巧，儘管如此，接面漏電流並沒有因此降低太多，因此，到了奈米製程，鉗頭架構使得頭電源線降低搭配浮接位元線已呈現一個趨勢因為次臨界漏電流、閘極漏電流和接面漏電流都能因此降低許多。
為了要節省甦醒時間和甦醒功率，我們混合了鉗地架構、鉗頭架構以及浮接位元線的技巧，此外，為了使得細胞內的資料不會流失，細胞的偏壓就必須小心設計，本論文中，我們提出了一個具有溫度警覺功能的偏壓架構而且兼顧了細胞穩定性即使製程、電壓和溫度變異發生時。我們提出了利用記憶體陣列中的一個複製欄來達到追蹤記憶體陣列的製程飄移以及溫度變異，且其額外的面積消耗和功率消耗都低於二個百分比。
一個由三萬兩千字元所組成的靜態隨機存取記憶體陣列使用了六五奈米互補金氧半技術製造來驗證我們的想法，量測結果顯示在高溫時我們能達到八十百分比的漏電流降低量，並且，使用我們提出架構的漏電流量測分布也比原先的漏電流分布來得窄。

Leakage has become pronounced as technology shrinks to nanometer scale. A large portion of SOC power dissipation directly comes from on-die SRAM leakage power. Low-er rail-to-rail voltage is an effective method to reduce SRAM array leakage. For deep sub-micron technology, footer is a common technique to raise the source line of pull-down NMOS and reduce both sub-threshold leakage and gate leakage. Nevertheless, junction leakage still remains and becomes worse for nanometer technology. Therefore, header combined with floating bit-lines becomes a trend to lower SRAM cell bias because it can reduce junction leakage aggressively. In order to save wake up time and wake up power, we use a hybrid clamping structure composed of footer, header, and floating bit-lines due to simultaneous wake up behaviors. Besides, it should be carefully controlled to maintain sufficient cell stability, avoiding potential data loss. In this work, we propose a thermal aware leakage reduction scheme and also concern the data retention issue with PVT varia-tion tracking. A 32kb SRAM macro has been fabricated in 65nm bulk CMOS technology to verify the idea of this work. The measurement results demonstrate that the SRAM array leakage achieves above 80% reduction at high temperature. In addition, SRAM array lea-kage distribution becomes narrower in our scheme compared to original one.

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