快閃型記憶體問世至今超過二十年，在市場迫切的需求下已成為非揮發性記憶體的主流產品，廣泛應用於嵌入式、攜帶式的電子產品之中，其中NAND型快閃記憶體架構為巨量資料儲存的最佳解決方法。由於NAND型快閃記憶體儲存單元密度高，容易受到元件操作干擾，因而造成元件耐久度及資料保存度衰減，寫入及抹除操作所施加在元件上的電性應力，會使穿隧氧化層產生缺陷，減少元件的使用壽命。這些被捕獲在氧化層中的電荷，影響浮動閘極與基板間的位能差，亦會影響寫入與抹除時的效率，令寫入臨界電壓飄移導致讀取視窗變小。當氧化層中的電荷累積到一定量時，會在浮動閘極、穿隧氧化層及基板間形成導通路徑，致使浮動閘極中的電子穿隧離開浮動閘極，因為浮動閘極為多晶矽材質，一旦該導通路徑形成，電子必將完全流失，造成資料毀損。
從之前的研究指出溫度與寫入/抹除間的延遲時間，能夠幫助避免錯誤位元的提升以及導通路徑的形成。此外，本論文還試圖以反向陣列加入寫入電壓，以期能有改變元件修復特性的結果，實驗以1X奈米NAND型快閃記憶體測試晶片作為實驗樣品，以改變寫入/抹除操作的條件來探討延遲時間、溫度及擬讀取循環對元件耐久度的影響；最後，論文討論提出反向寫入/抹除對元件特性改變的分析。

With the urgent demand in the market, flash memories have already been the mainstream technology in nonvolatile memories for decades and widely applied in embedded or portable electronics. Among the various types of flash memories, NAND flash memories provide the best solution in mass data-storage applications. In high-density NAND flash device, compact cells are subject to more stress and interferences, meanwhile, the reliability of these device in their endurance and retention emerges. During program and erase operation, electrical stress of the tunnel oxide generates defects, leading to a reduced lifetime during cycling endurance. These defects change the potential energy between floating gate and substrate and reduces the program/erase efficiency during operations. As trapped charges accumulate in the tunneling oxide layer, the programming characteristics may also shift. In addition, the stress-induced defects induce enhanced make charge lost through trap-assisted tunneling.
Prior studies revealed that the cycling time and operation temperature both affect the charge-detrapping process and fail bits count during program/erase cycling endurance test. To further improve the recovery effect on the cells, we also study the effect of reverse side programming schemes. The experiments are based on 1X nm NAND flash testing chip as samples. The effect of operational parameters, delay time, dummy read reverse programming are investigated in this work.

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