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研究生: 陳衍昊
Chen, Yen-Hao
論文名稱: 考量多核系統下執行的模板應用程式利用動態資料搬移來消除記憶庫干擾
Dynamic Data Migration to Eliminate Bank-level Interference for Stencil Applications in Multicore Systems
指導教授: 黃婷婷
Hwang, TingTing
口試委員: 金仲達
King, Chung-Ta
黃俊達
Huang, Juinn-Dar
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2014
畢業學年度: 102
語文別: 英文
論文頁數: 40
中文關鍵詞: 動態排程模板應用程式記憶庫衝突記憶體干擾
外文關鍵詞: dynamic scheduling, stencils, bank conflicts, memory interference
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  • 模板應用程式的特性是不斷地使用自身以及鄰近的點來進行相同的運算。新穎的自動轉換編譯技術可以有效率的產生磁磚式平行化模板應用程式。動態排成平行化模板應用程式大幅度的增加系統效能,然而,因為較少的閒置的核心以及較多的記憶體需求在一個時間被送至記憶體,造成了記憶體干擾問題惡化。傳統作業系統虛擬頁著色方法將記憶體虛擬頁分開來,但是沒辦法有效消除動態排成平行化模板應用程式的記憶體干擾。實驗結果顯示,與原本動態排成平行化模板應用程式相比,在八個核心、四個記憶庫的系統上面,我們的方法增快系統效能7%;在十六個核心、四個記憶庫的系統上面,則是增快9.3%。


    A stencil computation repeatedly updates each point of a d-dimensional grid as a func-tion of itself and its near neighbors. Modern automatic transformation compiler framework can generate ecient tiling parallel stencil codes. Dynamically scheduling parallel stencils signi cantly improves system performance. However, memory contention problem exacer-bates because of less idling cores and more memory requests sent to the DRAM memory in the same period of time. Traditional OS page coloring method which partitions the memory pages in advance can not alleviate the memory contention in dynamic scheduling parallel stencils. To address this issue, we provide a new software/hardware cooperation dynamic data migration method. Experimental evaluation in a 8-core x86 system shows that our method can improve the system performance by 7% as compared with dynamic scheduling stencils in 8-cores 4-memory banks system and by 9.3% in 16-cores 4 memory banks system.

    1 Introduction 1 2 Previous Work 5 2.1 OS-Level Thread Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Memory Page Mapping Scheme . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Compiler-Based Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 Scheduling Algorithms for Memory Controller . . . . . . . . . . . . . . . . . 7 3 Motivation 9 4 Methodology 15 4.1 Overview of System Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 Updated-and-Reused Aware Page Allocation Policy in OS . . . . . . . . . . 18 4.3 Migrate-On-Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 Memory Controller for Bank-level Interference Elimination . . . . . . . . . . 21 5 Experimental Results 25 5.1 Simulation Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 E ect of the Number of Entries in Mapping Table . . . . . . . . . . . . . . . 29 5.4 E ect of the Number of Banks in a Group . . . . . . . . . . . . . . . . . . . 30 5.5 Scalability with Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 Conclusion

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