本論文是利用一個與互補式金氧半場效電晶體 (CMOS) 製程相容的汲極延伸金氧半場效電晶體 (DEMOS) 高壓元件，透過 RESURF 模型、崩潰電壓模型來探討其元件的特性。主要分成兩個部分，第一個部分是探討 RESURF 的行為。包含兩種 RESURF 的來源: P 型井與多晶矽盤 (poly plate)；兩者皆可降低等效的 N 型載子濃度，進而增加崩潰電壓值。文中推演一個 P 型井的 RESURF 方式，獲得等效 N 型載子濃度的減少量與 P 型井到堆積區域距離方程式。另外，利用保角映像 (conformal mapping) 法建構一個多晶矽盤的 RESURF 模型。探討等效 N 型載子濃度的減少量與元件的汲極延伸指狀區寬度 (zo)，多晶矽盤與汲極延伸指狀區的間隙 (zd) 與淺溝槽絕緣體 (STI) 深度 (ys) 之行為。
另一部分是研究崩潰電壓的二維模型。利用保角映像法建構一個二維崩潰電壓模型。調查崩潰電壓與元件的堆積區域 (xa) 與淺溝槽絕緣體深度 (ys) 之關係，並藉此來準確地估算崩潰電壓值。經由 RESURF 模型能準確地估算等效 N 型載子濃度，並且結合二維崩潰電壓模型，得到之崩潰電壓估算值與實驗值及模擬值相當吻合.

In the thesis, a CMOS compatible high-voltage STI DEMOS transistor is fabricated and its electrical characteristics studied. Two major topics are under investigated. The first topic is RESURF model. There are two RESURF sources: the p-well and the poly plate. Both the p-well and the poly plate served as a RESURF are adopted to enhance the breakdown voltage by reducing the effective doping concentration. A RESURF method, which is related to the overlap/underlap Op between the p-well and the STI, is derived for p-well. Besides, the other RESURF model, which the reduction of the doping concentration theoretically is related to the width (zo) of the drain extension finger, the gap (zd) between the poly plate and the drain extension finger, and the STI depth ys, is derived by the conformal mapping for poly plate.
The second topic is a two-dimensional breakdown down model, which is adapted for both full STI DEMOS and finger-type STI DEMOS. The conformal-mapping method is used to evaluate the breakdown voltage of this two-dimensional STI DEMOS structure theoretically. A breakdown voltage model, which relates the breakdown voltage to the width of the accumulation region xa and the STI depth ys, is derived. Combined with the effective doping concentration by RESURF model, the predictions of this breakdown voltage model agree very well with the experimental data and the TCAD simulations.

[1] A. Moscatelli, A Merlini, G. Croce, P. Galibiati and C. Contiero, “LDMOS Implementation in a 0.35μm BCD Technology (BCD6),” In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 2000, pp.323-326.
[2] S. Pendharkar, R. Pan, T. Tamura, B. Todd and T. Efland, “7 to 30V state-of-art power device implementation in 0.25μm LBC7 BiCMOS-DMOS process technology,” In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 2004, pp.419-422.
[3] P. Hower, J. Lin, S. Pendharkar, B. Hu, J. Arch, J. Smith and T. Efland, “A Rugged LDMOS for LBC5 Technology,” In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 2005, pp.159-162.
[4] H. Puchner, S. Lee, L. Hinh, and J. Jang, “High Voltage LDMOS Transistors utilizing a Triple Well Architecture,” In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 2007, pp. 201-404.
[5] M. Shrivastava, M. S. Baghini, H. Gossner and V.R. Rao, “Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices,” IEEE Trans. Electron Devices, vol. 57, pp. 448-457, Feb. 2010.
[6] J. Sonsky and A. Heringa “Dielectric Resurf: breakdown voltage control by STI layout in standard CMOS, Proceedings IEDM 2005, pp.385-388, 2005.
[7] A. Heringa, J. Sonsky, J. P. Gonzalez, R. Y. Su and B. Y. Chiang, “Innovative lateral field plates by gate fingers on STI regions in deep submicron CMOS”, In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 2008, pp.271-274.
[8] M. A-Khalil, T. Letavic, J. Slinkman, A. Joseph, A. Botula and M. Jaffe, “Lateral Tapered Active Field-Plate LDMOS Device for 20V Application in Thin-Film SOI,” In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 2012, pp.253-255.
[9] J. Jang, K. H. Cho, D. Jang, M. Kim, C. Yoon, J. Park, H. Oh, C. Kim, H. Ko, K. Lee, and S. Yi, “Interdigitated LDMOS,” In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 2012, pp. 245-248.
[10] J. F. Chen, K. S. Tian, S. Y. Chen, K. M. Wu, J.R. Shih and K. Wu, “An Investigation on Anomalous Hot-Carrier-Induced On-Resistance Reduction in n-Type LDMOS Transistors,” IEEE Trans. Device and materials Reliability, vol. 9, pp. 459-464, Sep. 2009.
[11] J. F. Chen, J. R. Lee, K. M. Wu, T. Y. Huang and C. M. Liu “Mechanism and Improvement of On-Resistance Degradation Induced by Avalanche Breakdown in Lateral DMOS Transistors,” IEEE Trans. Electron Devices, vol. 55, pp. 2259-2262, Feb. 2008.
[12] J. F. Chen, S. Y. Chen, K. M. Wu, J. R. Shih and K. Wu, “Convergence of Hot-Carrier-Induced Saturation Region Drain Current and On-Resistance Degradation in Drain Extended MOS Transistors,” IEEE Trans. Electron Devices, vol. 56, pp. 2843-2847, Nov. 2009.
[13] S. K Samanta, N. Patel, K. N. ManjulaRani, and K. Jang, “Stress Voltage Dependence HCI Induced Traps Distribution in 60V LDNMOS,” International Integrated Reliability Workshop, 2009, pp. 120-123
[14] S. Reggiani, G. Barone, S. Poli, E. Gnani, A. Gnudi, G. Baccarani, M. Y. Chuang, W. Tian and R. Wise, “TCAD Simulation of Hot-Carrier and Thermal Degradation in STI-LDMOS Transistors,” IEEE Trans. Electron Devices, vol. 60, pp. 691-698, February 2016.
[15] J. Zhu, W. Sun, H. Chen and S. Lu, “Investigation on Electrical Degradation of High Voltage nLDMOS After High Temperature Reverse Bias Stress,” IEEE Trans. Device and materials Reliability, vol. 14, pp. 651-656, June 2014.
[16] K. Cho, S. Ko, F. Machida, J. Kim, J. Jang, U. Kwon, K. H. Lee and Y. Park, “Investigation of HCI Reliability in Interdigitated LDMOS,” In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 2015, pp.69-72.
[17] K. P. Brieger, E. Falck, and W. Gerlach, “The Contour of an Optimal Field Plate-An Analytical Approach,” IEEE Trans. Electron Devices, vol. 35, pp. 684-688, Jan. 1988
[18] S. K. Chung, D. C. Yoo, and Y. I. Choi, “An Analytical Method for Two-Dimensional Field Distribution of a MOS Structure with a Finite Field Plate,” IEEE Trans. Electron Devices, vol. 42, pp. 192-194, Jan. 1995.
[19] P. Habas, Analysis of Physical Effects in Small Silicon MOS Devices, Technischen Universitat Wien, 1993.
[20] B. J. Baliga and S. K. Ghandhi, “Analytical solutions for the breakdown voltage of abrupt cylindrical and spherical junctions,” Solid-State Electrics, 1976 Vol. 19, pp. 739-744.
[21] R. Stengl and E. Falck, “Surface Breakdown and Stability of High-Voltage Planar Junctions,” IEEE Trans. Electron Devices, vol. 38, pp. 2181-2188, Sep. 1991.
[22] T. Sakuda, N. Sadachika, Y. Oritsuki, M. Yokomichi, M. Miyake, T. Kajiwara, H. Kikuchihara, U. Feldmann, H. J. Mattausch and M. M. Mattausch, “Effect of Impact-Ionization-Generated Holes on the Breakdown Mechanism in LDMOS Devices” International Conference on Simulation of Semiconductor Processes and Devices, 2009, pp. 1-4.
[23] A. S. Grove, O. Leistiko and W. W. Hooper, “Effect of Surface Fields on the Breakdown Voltage of Planar Silicon p-n Junctions,” IEEE Trans. Electron Devices, ED-14, pp. 157-162, Mar. 1967.
[24] A. Rusu and C. Bulucea, “Deep-Depletion Breakdown Silicon-Dioxide/SiIicon Capacitors,” IEEE Trans. Electron Devices, vol. 26, pp. 518-524, March 1979.
[25] Z. Zheng, W. Li and P. Li, “Potential floating layer SOI LDMOS for breakdown voltage enhancement,” International Conference on Solid-State and Integrated Circuit Technology Proceedings, pp. 1-3, 2012.
[26] R. Stengl and E. Falck, “Surface Breakdown and Stability of High-Voltage Planar Junctions,” IEEE Trans. Electron Devices, vol. 38, pp. 2181-2188, September 1991.
[27] Z. Parpia and C. A. T. Salama, “Optimization of RESURF LDMOS Transistors: An analytical Approach,” IEEE Trans. Electron Devices, vol. 37, pp. 789-796, Mar. 1990.
[28] M. Zitouni, F. Morancho, H. Tranduc, P. Rossel, J Buxo, I. Pages and S Merchant, “A new lateral power MOSFET for smart power ICs: the “LUDMOS concept”, Microelectron. J., vol. 30, no.6, pp. 551-561, Jun. 1999.
[29] J. A. Appels and H. M. J. Vaes, “High Voltage Thin Layer Devices (RESURF Devices),” in Proc. Intl. Electron Devices Meeting, pp. 238-241, 1979.
[30] T. Efland, S. Malhi, W. Bailey, O. K. Kwon, and W. T. Ng, “An Optimized RESURF LDMOS Power Device Module Compatible with Advanced Logic Processes,” Proc. Intl. Electron Devices Meeting, pp. 237-240, 1992.
[31] A. W. Ludikhuize, “A Review of RESURF Technology,” In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 2000, pp. 11-18.
[32] T. Miyoshi, T. Tominari, H. Fujiwara, T. Oshima, and J. Noguchi, “Design of a Reliable p-Channel LDMOS FET with RESURF Technology,” IEEE Trans. Electron Devices, vol. 61, pp. 1451-1456, May 2014.
[33] K. Zhou, X. Luo, Q. Xu, Z. Li, and B. Zhang, “A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific ON-Resistance,” IEEE Trans. Electron Devices, vol. 61, pp. 2466-2472, Jul. 2014.
[34] X. Zhou, M. Qiao, Y. He, Z. Wang. Z, Li, B. Zhang, “Back-Gate Effect on Ron.sp and BV for Thin Layer SOI Field p-Channel LDMOS,” ” IEEE Trans. Electron Devices, vol. 62, pp. 1098-1104, Jun. 2015.
[35] W. Zhang, B. Zhang, M. Qiao, L. Wu, K. Mao, and Z. Li , “A Novel Vertical Field Plate Lateral Device With Ultralow Specific On-Resistance,” IEEE Trans. Electron Devices, vol. 61, pp. 518-524, Feb. 2014.
[36] S. Gao, J. Chen, D. Ke and L. Liu, “Analytical Model for Surface Electrical Field of Double RESURF LDMOS with Field Plate,” International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006, pp. 1324-1326.
[37] B.K. Boksteen, S. Dhar2, A. Heringa, G. E. J. Koops and R. J. E. Hueting, “Extraction of the Electric Field in Field Plate Assisted RESURF Devices,” In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 2012, pp. 145-148.
[38] W. Zhang, B. Zhang, M. Qiao, L. Wu, K. Mao, and Z. Li , “A Novel Vertical Field Plate Lateral Device With Ultralow Specific On-Resistance,” IEEE Trans. Electron Devices, vol. 61, pp. 518-524, Feb. 2014.
[39] C. B. Goud and K. N. Bhat, “Analysis and Optimal Design of Semi-Insulator Passivated High-Voltage Feld Plate Structures and Comparison with Dielectric Passivated Structures,” IEEE Trans. Electron Devices, vol. 41, pp. 1856-1864, October 1994.
[40] T. Minchin; S. Gene; T. J. Ruey; Y. Shaoming, “Improvement of Electrical Characteristics in LDMOS by the Insertion of PBL and Gate Extended Field Plate Technologies,” International Conference on Electronic Measurement & Instrument, 2011, pp. 5-9.
[41] C. C. Wei, H. C. Chiu, W. S. Feng, “High-Linearity Performance of 0.13-μm CMOS Devices Using Field-Plate Technology,” IEEE Trans. Electron Device Letters, vol. 27, pp. 843-845, October 2006.
[42] C. A. Neugebauer, J. F. Burgess, R. E. Joynson, “I-V characteristics of MOS capacitors with polycrystalline silicon field plates,” J. Appl. Phys.,, vol. 43, pp. 5041-5044, December 1972.
[43] T. Letavic, S. Sharma, R. Cook, R. Brock, A. Gondal, C. Mandhare, W. V. Noort, “A Field-Plated Drift-Length Scalable EDPMOS Device Structure,” In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 2009, pp.108-111.
[44] A. S. Kluchnikov, A. Y. Krasukov, “Application of Field Plate to Increase Breakdown Voltage of DMOS,” Siberian Russian Workshop and Tutorial on Electron Devices and Materials, 2007, pp.107-108.
[45] W. Sun, Y. Yi, S. Lu, L. Shi, “Analysis on the Surface Electrical Field of High Voltage Bulk-Silicon LEDMOS with Multiple Field Plates,” International Conference on Solid-State and Integrated Circuits Technology, 2004, pp.353-356.
[46] K. J. Binns and P. J. Lawrence, Analysis and Computation of Electric and Magnetic Field Problems. New York: Pergamon, 1973.
[47] R. Zhu, V. Parthasarathy, V. Khemka, A. Bose and T. Roggenbauer, “Implementation of High-Side, High-Voltage RESURF LDMOS in a sub-half Micron Smart Power Technology,” In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 2001, pp.403-406.
[48] A. Nezar; C. A. T. Salama, “Optimization of the Breakdown Voltage in LDMOS Transistors using internal Field Rings,” In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 1991, pp.149-153.
[49] C. A. Neugebauer, J. F. Burgess, R. E. Joynson, “Avalanche Breakdown in Polycrystalline Silicon Films,” Reliability Physics Symposium, 1973, pp. 163-169.
[50] A. D. Wunsch, Complex Variables with applications, Pearson Addison Wesley, 2005.
[51] R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, 2nd edition, John Wiley & Sons, 1976.
[52] W. Yao, G. Gildenblat, C. C. McAndrew, and A. Cassagnes , “Compact Model of Impact Ionization in LDMOS Transistors,” IEEE Trans. Electron Devices, vol. 59, pp. 1863-1869, Nov. 2012.
[53] M. I. Mahmud, Z. Ç. Butler, P. Hao, P. Srinivasan, F. C. Hou, X. Cheng, B. L. Amey, and S. Pendharkar, “A Physics-Based Analytical 1/f Noise Model for RESURF LDMOS Transistors,” IEEE Trans. Electron Devices, vol. 60, pp. 677-683, Feb. 2013.
[54] A. Bazigos, F. Krummenacher, J. M. Sallese, M. Bucher, E. Seebacher, W. Posch, K. Molnár, and M. Tang, “A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET,” IEEE Trans. Electron Devices, vol. 58, pp. 1710-1721, Jun. 2011.
[55] W. Wang, B. Tudor, X. Xi, W. Liu and F. J. Lee, “An Accurate and Robust Compact Model for High-Voltage MOS IC Simulation,” IEEE Trans. Electron Devices, vol. 60, pp. 662-669, Feb. 2013.
[56] X. Zhou, M. Qiao, Y. He, Z. Wang, Z. Li, and B. Zhang, “Back-Gate Effect on RON,sp and BV for Thin Layer SOI Field p-Channel LDMOS,” IEEE Trans. Electron Devices, vol. 62, pp. 518-524, April 2015.
[57] X. Luo, T. Lei, Y. Wang and B. Zhang, “A Novel High Voltage SOI LDMOS with Buried N-layer in a Self-isolation High Voltage Integrated Circuit,” In Proc IEEE Int. Symp. Power Semicond. Devices ICs, 2010, pp. 265-268.
[58] S. Schwantes, T. Florian, M. Graf, F. Dietz and V. Dudek, “Analysis of the back gate effect on the breakdown behavior of SOI LDMOS transistors,” Solid-State Device Research conference, 2004, pp. 253-256.
[59] Y. Guo; Z. Li; B. Zhang, “A new two dimensional analytical breakdown model of SOI RESURF devices,” International Conference on Communications, Circuits and Systems, 2007, pp. 1278-1282.
[60] M. N. Marbell, S. V. Cherepko, J. C. M. Hwang, M. A. Shibib, W. R. Curtice, “Modeling and Characterization of Effects of Dummy-Gate Bias on LDMOSFETs,” IEEE Trans. Electron Device Letters, vol. 54, pp. 580-588, March 2007.
[61] J. Victory, C. C. McAndrew, J. Hall, M. Zunino, “A Four-Terminal Compact Model for High Voltage Diffused Resistors with Field Plated,” IEEE Journal of Solid-State Circuits, 1998, pp.1453-1458.
[62] S. K. Ghandhi, Semiconductor Power Devices: Physics of Operation and Fabrication Technology, John Willey & Sons, 1977.