本論文提出應用於生物訊號的一個十二位元每秒十萬次取樣頻率的類比數位轉換器，此轉換器利用TSMC 0.18um製程來設計，操作電壓為1.8V。主要電路架構分為取樣保持電路、數位類比轉換器、比較器以及連續逼近數位電路。取樣保持電路使用拔靴開關(bootstrapped)讓電路的線性度提高並減少訊號失真。比較電路由動態再生閂鎖組成，正回授加快比較器轉換速度。在數位類比轉換器中使用分離式電容陣列(split capacitor array)來減少整體的電容值和平均功耗。連續漸進控制邏輯電路使用一組位移暫存器控制轉換程序與一排D型正反器分別控制分離式電容陣列。
由於製程的不匹配以及佈局上造成的誤差會導致輸出數位訊號精準度下降，在此提出一個在轉換器內部做自我校正功能的電路，降低製程誤差對轉換器所造成的影響。本篇論文針對比較器及電容陣列分別加上校正電路用來提高精準度。在電容陣列的校正中，利用電荷重新分佈的概念將權重最小的兩個相同電容做比較，將較小的電容補償至與較大的電容權重相同，接這將這個電容當成單位電容，重新產生一組新的二進位制的電容陣列，讓電容陣列因為製程造成的誤差經由校正後仍可維持我們需要的比例關係。在比較器校正電路中，由於輸入端的偏移誤差並非定值且非線性，不同的輸入電壓會造成不同的偏移誤差，我們將輸入電壓分成幾個區段，並且利用片段線性逼近的方式去預測不同輸入電壓時之偏移誤差，使用電流模式做補償，減少比較器輸入端在不同輸入電壓時所造成的誤差。在此類比數位轉換器正常操作模式之前多創造一個校正模式，用來作比較器及電容陣列的校正，並將校正後的數位碼存取至正反器中，在正常操作模式中澤直接利用這些數位碼作校正，不需耗費任何額外的時間。經過校正過後的類比數位轉換器，當輸入訊號為100KS/s，SNDR為66.78dB，有效位元數為10.8位元。微分非線性誤差為0.69 LSB，積分非線性誤差為0.86 LSB。
相對於現有校正方法，本論文所提出的校正機制可適用於任何輸入電壓，有效預測當時的誤差並將此誤差降到最低。一開始利用數位電路校正並存取校正數位碼，之後只需讀取此數位值便可完成校正，有效節省每次校正所需消耗的功率及時間。另外和傳統類比校正方法比較，使用數位電路取代電容進行校正也可省下大量面積。除此之外，由於數位校正方法用使用到大量的數位邏輯電路，越先進的製程基本數位邏輯閘較小，相對可以減少整個數位校正電路的面積。

This thesis presents a 12-bit 100KS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The A/D converter is designed in TSMC 0.18um CMOS process and operates at a supply voltage of 1.8V. The SAR A/D converter includes track-and-hold (T/H) stage, comparator, digital-to-analog converter and SAR control logic. Bootstrapped switch is used in S/H for improving circuit linearity and reducing the signal distortion. The comparator is composed of a dynamic latched regenerative circuit which gives comparator output better accuracy and higher speed because of positive feedback. Split capacitor array is used in D/A converter to decrease the total capacitance and save average power. Finally, the SAR control logic circuit uses a form of shift-registers-control conversion process and a row of D flip-flops for controlling the spilt capacitor array.
The performance of the converter would be degraded due to the process variation and device mismatches. This thesis proposes self-correction circuits for comparator and D/A separately capacitor array calibration, larger LSB is chosen as a new reference unit capacitor, and produce a new binary-weighted capacitor array by charge redistribution. After D/A calibration, comparator input offset voltage needs to be calibrated and canceled. Because this offset is not linear, a new calibration method is proposed that divides input voltage into multiple windows and use piecewise linear approximation to predict and reduce input offset. Before normal operation, calibration mode is created to do DAC and comparator calibrations. Digital calibration codes are saved in latches, and these digital codes can be used in normal operation mode without wasting other clock cycles. After digital calibration, when sampling rate is 100KS/s, the SNDR is found to be 66.78dB, and ENOB is 10.8 bits. DNL and INL are found to be 0.69 and 0.86 LSB, respectively.
Comparing to other calibration methods, the proposed calibration can predict and reduce offset for full range input voltages, thus has higher accuracy than other digital calibration methods. Since the digital calibration is used, calibration results are saved in flipflops and can be reused repeatedly. Smaller chip and shorter normal mode operation can be achieved. In addition, digital circuit is easier to scale and thus needs smaller area for advanced technologies.

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