隨著電子構裝之晶片數目增加及電子構裝體積縮小，多晶片模組構裝之散熱效能愈為重要。在不改變構裝結構及元件材料下，欲提升多晶片模組構裝熱效能，晶片之最適化擺置為一重要研究方向。本論文旨在針對具不同數目及發熱功率晶片之多晶片模組構裝，在自然對流環境下，探討晶片擺置之最適化法，以提高多晶片模組構裝之散熱效能。
本論文所提出之最適化法分別為直接最適化法、間接最適化法、混合式最適化法及精進型混合式最適化法。直接最適化法係直接利用ANSYS®有限單元熱傳分析計算不同晶片擺置下之總晶片接面溫度，再結合遺傳演算法之演化搜尋，求得晶片最適擺置。間接最適化法係結合ANSYS®有限單元熱傳分析及以回應表面法為基礎之修正型疊加法，快速建立多晶片模組構裝之晶片接面溫度回應表面，再結合序列二次規劃法求得晶片最適擺置及總晶片接面溫度。混合式最適化法乃結合直接最適化法與間接最適化法之優點，利用ANSYS®有限單元熱傳分析及遺傳演算法之全域搜尋特性，以回應表面法為基礎，建立晶片接面溫度方程式，並利用序列二次規劃法快速求取晶片最適擺置。而精進型混合式最適化法乃進一步結合變數設計範圍縮減法，根據所求得之較優晶片擺置設計增加新晶片擺置設計，不斷迭代求取新回應表面及計算最小總晶片接面溫度之步驟，以精進混合式最適化法之效能。
藉由數種多晶片模組構裝，本論文分別評比所提出各種晶片擺置最適化法之效能。直接最適化法因經過多次演化，而使用大量計算量，但卻只能得較優解。間接最適化法所提出之以回應表面為基礎之修正型疊加法，因建立了包含晶片發熱功率及晶片位置影響之晶片接面溫度方程式，不僅具傳統回應表面法之準確性，且能大量減少數據量。混合式最適化法結合直接最適化法及間接最適化法之特點，大幅降低了所需數據量，故計算效率遠高於傳統回應表面法、直接最適化法及間接最適化法，唯所建立之回應表面尚不能準確計算晶片最適擺置下之總晶片接面溫度。精進型混合式最適化法所需數據量雖略多於混合式最適化法，但遠小於傳統回應表面法、直接最適化法及間接最適化法，不但能準確、快速求得晶片最適擺置及總晶片接面溫度值，且因可透過停止條件之調整，尤適用於具多數晶片之多晶片模組構裝散熱分析。
對於晶片之最適擺置，除散熱外，電訊方面考量亦相當重要。本論文所提出之最適化法可進一步結合電訊限制條件，使其應用延伸至同時考慮散熱及電訊效應之多晶片模組構裝晶片最適擺置設計，更切合實務。此外，以本論文之成果為基礎，結合熱應力分析，亦可探討多晶片模組構裝於晶片最適擺置下之可靠度，以作為散熱增益設計之參考。

As the number of chips within electronic packaging increases while their feature sizes shrink, the thermal performance of multichip modules (MCMs) becomes increasingly critical. To upgrade the thermal performance of MCMs without changing package structure and materials, optimal chip placement is an important research aspect. Therefore, this work aims at enhancing the thermal performance of MCMs under natural convection by optimizing the chip placement. To attain the goal, novel chip placement optimization schemes are proposed.
The chip placement optimization schemes proposed include the direct optimization scheme, the indirect optimization scheme, the hybrid optimization scheme and the modified hybrid optimization scheme. The direct optimization scheme directly calculates the total chip junction temperature of a MCM under various chip placements by ANSYS® finite element thermal analysis and obtains the optimal chip placement through genetic algorithm evolution. The indirect optimization scheme combines the ANSYS® finite element thermal analysis and a response surface based modified superposition method to effectively construct the response surfaces of chip junction temperature. With the constructed chip junction temperature response surfaces and sequential quadratic programming, an optimal chip placement and total chip junction temperature can be achieved. The hybrid optimization scheme combines the merits of the direct optimization scheme and the indirect optimization scheme. It integrates the ANSYS® finite element thermal analysis, a global search heuristic algorithm, genetic algorithm, and a response surface method to construct the chip junction temperature equations. The chip junction temperature equations constructed are adopted in sequential quadratic programming to find the optimal chip placement. The modified hybrid optimization scheme is the modification of the hybrid optimization scheme. The concept of design space reduction is employed. The procedures of adding new chip placement designs, constructing new chip junction temperature equations and finding minimum total chip junction temperature are repeated to upgrade the efficiency of the hybrid optimization scheme.
To demonstrate the effectiveness of the proposed optimizaiton schemes, several thermal dissipation analysis problems associated with two types of MCM are performed. The results obtained show that the direct optimization scheme can only find better solution after massive computations. The response surface based modified superposition method proposed in the indirect optimization scheme can construct chip junction temperature equations that take the influence of chip power and placement into account. It has the same accuracy as the conventional response surface method with less computation. The hybrid optimization scheme largely reduced the computation time toward optimization and its computational efficiency is much higher than the conventional response surface method, the direct optimization scheme and the indirect optimization scheme. However, the constructed response surface is still insufficient to provide accurate total chip junction temperature under the optimal chip placement found. Although the modified hybrid optimization scheme needs a few more computations than hybrid optimization scheme, but its computational efficiency is much higher than the conventional response surface method, the direct optimization scheme and the indirect optimization scheme. It can calculate the optimal chip placement and total chip junction temperature effectively and accurately. Through an appropriate adjustment of the tolerance taken, the modified hybrid optimization scheme is especially useful for larger-scale MCM thermal design problems.
With the consideration of electrical requirement, this work can be further devoted to deal with the optimization of chip placement of MCMs considering both thermal and electrical problems. Moreover, by incorporating the current result with thermal stress analysis, the reliability of MCMs can also be analyzed and used as a guideline for the thermal management of MCMs.

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