隨著現今科技的演進，智慧型手機以及平板電腦已將取代筆記型電腦與個人數位助理(Personal Digital Assistant, PDA)裝置，因為其可提供行動網路、多媒體數位與內建全球定位系統(Global Positioning System, GPS)等功能，而這些產品的問世為顯示器與半導體的市場帶來了大幅度的成長，也因此客戶們對於具備高速資料傳輸的產品有了更多的需求，所以顯示裝置具備薄邊框(narrow bezel)、低功耗、高速運算以及高信賴性等功能將可大量增加產品的普及性與銷售量。
為了達到顯示裝置對於薄邊框的需求，液晶顯示器(Liquid Crystal Display, LCD)中的閘極驅動電路(gate driver)使用非晶矽薄膜電晶體(Thin-Film-Transistor, TFT)設計已成為一個主要的趨勢，因為有成熟的顯示技術、低成本的製程與減少互補式金氧半(Complementary Metal-Oxide-Semiconductor, CMOS)積體電路(Integrated Circuit, ICs)的數量等優點，此外為了降低顯示裝置於靜態畫面顯示時所消耗的功耗，記憶體內嵌於畫素(Memorry-In-Pixel (MIP)的概念也被提出並使用薄膜電晶體所設計，然而設計薄膜電晶體的電路相對於CMOS電路主要面對到較低的載子傳輸能力以及高電壓驅動導致穩定度下降的兩個重要挑戰，而為了降低較低載子傳輸能力的限制，薄膜電晶體在佈局時會使用較大的面積推動面板內部的負載，但也不可避免造成電路具有較大的寄生(parasitic)效應，再加上薄膜電晶體電路的耐久度也是一個需要解決的問題，因為當薄膜電晶體經過長期電壓的施加，薄膜電晶體的主動層會產生大量缺陷(defects)進而使電晶體的臨界電壓偏移減少了顯示產品的耐久度，所以前述的兩項因素為薄膜電晶體電路的主要設計挑戰。
總結前述的電路設計的挑戰即為本研究論文的主題:設計與實現玻璃基板上之電路及其於顯示系統的應用，本論文的章節包括：(1) 設計低功耗閘極驅動電路、(2) 設計單級多輸出閘極驅動電路於薄邊框面板的應用、(3) 設計高信賴補償性閘極驅動電路於車載面板以及中大型尺寸面板的應用(4)數位畫素記憶體電路於低功耗顯示器的應用。
本論文第二章提出關於電路設計製作的流程、非晶矽薄膜電晶體元件量測、參數萃取以及元件模型建立。
本論文第三章提出一種新型的閘極驅動電路並成功以非晶矽薄膜電晶體設計與製作於4.5吋WVGA(800xRGBx480)規格的面板且通過合作公司的穩定度測試。此電路利用四個時序訊號(clock)提供閘極驅動電路並複製其輸出(單一充放電)，此方法有別於一般閘級驅動電路需要上升和下降電晶體區塊，大大減少閘級驅動電路布局所需的面積。再者，動態功耗的減少也因下降電晶體區塊的面積縮減而減少。此外，正反掃功能的添加也有助於滿足客戶的需求以及智慧型面板翻轉的功能。
本論文第四章提出一種新型的窄邊框閘級驅動電路並成功降低面板邊框從1.2mm降於1mm左右。此電路運用抗雜訊電路區塊的共享架構，成功將單級單輸出的閘級驅動電路提升輸出數量至單級雙輸出以及三輸出。此方法有效的降低每級抗雜訊電路的使用電晶體顆數，進而有效減少閘級驅動電路佈局的面積。
本論文第五章提出兩種新型的閘級驅動電路並成功達成500小時高溫劣化測試仍能夠維持正常的運作。此電路運用門檻電壓補償裝置將非晶矽薄膜電晶體的劣化電壓回授到驅動閘級端去維持非工作狀態的抗雜訊效能。此外，利用clock時序訊號調整可降低關鍵劣化電晶體的工作時間而延長閘級驅動電路的壽命。
本論文第六章提出兩種非晶矽薄膜電晶體數位記憶體電路於低功耗應用的液晶顯示器之設計，此電路利用低成本的非晶矽薄膜電晶體設計畫素內部的記憶體來自我提供電壓給液晶在面板待機狀態下，透過內部記憶體電壓的供應來降低待機狀態下資料驅動電路的輸入頻率，進而減少IC所產生的功率消耗。此外，利用交流參考電壓以及電容耦合式的設計，可產生液晶所需要的正反轉訊號來避免液晶的過度劣化。
第七章總結本論文的研究成果，並提出數個接續本論文研究方向的研究題目。本論文所提出的各項新型設計，皆已搭配面板整合或實驗晶片加以驗證。此外本研究有數篇國際期刊與國際研討會論文發表，並有數項創新設計已提出中華民國及美國專利申請。

With current technology advancements, smart phones and tablet computers are fast becoming a viable alternative to PDAs and laptops, offering features such as mobile internet applications, multi-media functionality, and inbuilt GPS capabilities. The emergence of these products brings the progressive growing of display market. Therefore, display devices with narrow bezel, low power consumption, and high speed data capabilities are gaining the sale volume and popularity.
For the narrow bezel demands of display devices, gate driver circuit using thin-film-transistor (TFT) has become a main stream for the liquid crystal display (LCD) due to the mature manufacturing, low-cost processing, and reducing of complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs). Furthermore, the design of memory-in-pixel (MIP) using TFT is as well as proposed to meet the low power consumption of mobile displays, which provided a low power standby mode for continuous display of static images. Nevertheless, design of TFT driver encounters two main challenges which are the lower field-effect mobility and the reliability issue under high voltage stress as compared with CMOS transistors. In order to alleviate the low mobility restriction, the larger width of the main driving TFT is required to drive the panel, however it accompanies with large parasitic effects inevitably. In addition, the reliability issue of the TFT drivers is as well as a notable challenge. While TFT suffers long term high voltage stress, the defect-state creation will cause threshold voltage shifts to decrease the life time of the driver. Consequently, these characteristics increase the design challenge of TFT driver circuits.
The aforementioned design challenges of on-panel circuits for applications in display system form the motivation of this dissertation. The research topics of this dissertation including: (1) integrated gate driver with low power consumption in amorphous silicon (a-Si) technology, (2)single-stage-multi-outputs gate driver for narrow bezel panel application, (3)integrated gate driver with high reliability for medium and large size TFT-LCD or panel in car, (4)digital memory pixel circuit for panel with low power consumption .
In chapter 2, the process of circuit design、measurement of device if a-Si thin film transistor、parameter extraction and model building.
In chapter 3, a new integrated gate driver on array (GOA) has been successfully designed and fabricated by amorphous silicon (a-Si) technology for a 4.5-inch WVGA (800xRGBx480) TFT-LCD panel. The proposed circuit is designed with four clock signals to provide and copy outputs (single charging and discharging path) to gate driver. The layout area is reduced efficiently by this way compares to traditional gate driver which needs circuit blocks for pulling up and down. Moreover, dynamic power consumption is also reduced by small area for pull-down circuit block. Besides, bi-directional function is conducive to satisfy the demand of customers and function of screen rotation for smart panels.
In chapter 4, a new gate driver is designed and integrated in panel for lowering the panel bezel from 1.2mm to 1.0mm. Number of outputs could increase to dual outputs or triple outputs per stage successfully using the noise circuit block sharing. Amount of TFTs for noise free block could be reduced efficiently and then the layout area is also be decreased.
In chapter 5, two new type gate driver passed reliability tests for of the supporting foundry for 500 hours. Threshold voltage compensation block is added to maintain the performance of noise free by feedback degradation voltage to the a-Si TFT. Besides, the lifetime could be extended by modifying the clock signal to lower the duty cycle of key TFT.
In chapter 6, two new digital pixel circuit memories are designed for low power consumption TFT-LCD. A-Si pixel memory is embedded in panel to provide voltage to liquid crystal in the standby mode. The power consumption for IC is decreased because of lowering the inputting frequency of data driver by this way. Besides, inversion signals could be produced by AC reference voltages and capacitor coupling to avoid the degradation of liquid crystal.
Chapter 7 summarizes the main results of this dissertation. Some suggestions for the future works are also addressed in this chapter.
In this dissertation, several novel designs have been proposed in the aforementioned research topics. Measured results of the integrated panels and fabricated test chips have demonstrated the performance improvement. The achievements of this dissertation have been published or submitted to several international journal and conference papers. Several innovative designs have been applied for patents.

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