本研究目的是設計並實現所佔面積極小且具備良好特性的超寬頻（UWB）接收器前端電路以降低晶片成本。我們已完成小面積UWB LNA、寬頻被動式混波器及UWB接收機前端電路的設計與晶片實作。
LNA以TSMC 0.13-μm CMOS設計製作，採用電阻回授式架構並使用閘極電感提升頻寬。閘極電感是全電路唯一使用的電感，僅需0.4 nH就能有效提升電路頻寬並壓低高頻的雜訊。LNA核心電路所佔面積僅0.031 mm2。經量測，LNA頻寬涵蓋UWB 3.1-10.6GHz，在此頻段中增益為11-12.4 dB，NF為2.7-3.7 dB，S11 < -7.3 dB，在頻率為6GHz時IIP3為-3.8 dBm，電路的操作電壓為1.8 V，功率消耗為14.4 mW。
寬頻被動式混波器的實作採用TSMC 0.18-μm CMOS，電路包含一個前端放大器、混波開關（switch）及一個一階的主動低通濾波器。本電路核心面積為0.15 mm2。量測時LO功率選用5 Bm，量測結果顯示最大轉換增益為8.4 dB、頻寬為3-7 GHz，IF頻寬為210 MHz，在4 GHz時IIP3為-0.4 dBm，且不同端間隔絕良好，電路於1.8 V操作電壓下功率消耗為10.7 mW。
最後，UWB直接降頻接收機前端電路採用TSMC 0.13-μm CMOS設計製作，電路包含一個寬頻的差動式LNA及一個寬頻被動式混波器。我們在LNA輸出負載串上一個可用單一線圈提供差動電感負載的center-tapped電感來提升電路增益、NF及輸入匹配的頻寬，另外被動式混波器的前端放大器採用capacitive-peaking的技巧以提昇電路操作頻寬，整個電路就只有使用一個center-tap電感，主要電路的面積僅為0.22 mm2。本電路模擬結果顯示在UWB 3.1-10.6GHz頻段中，增益為21-22 dB，DSB NF為3.7-4.2 dB，6.6 GHz時IIP3為-15.3 dBm，在1.8 V操作電壓下功率消耗為32.8 mW。

The target of this research is to design and implement an ultra-wideband (UWB) direct-conversion receiver front-end occupied a small area with good performance to cost down. We have designed and implemented an UWB low noise amplifier (LNA), a wideband passive mixer and a UWB receiver front-end with compact sizes.
The LNA was implemented in TSMC 0.13 μm CMOS technology and based on the resistive-feedback architecture with bandwidth extension by gate inductive- peaking. The gate inductor with only 0.4 nH is the only coil used in this circuit which extends the bandwidth and lowers the noise at high frequencies of the LNA effectively. The core area of the LNA is 0.031 mm2. The measured bandwidth of the LNA covers UWB 3.1-10.6GHz and within this band the gain is 11-12.4 dB, the NF is 2.7-3.7 dB and S11 < -7.3 dB. The IIP3 measured at 6 GHz is -3.8 dBm. This LNA consumes 14.4 mW from a 1.8 V supply.
The wideband passive mixer implemented in TSMC 0.18 μm CMOS technology is composed of a pre-amplifier, mixing switches, and a 1st order active low-pass filter. The core area of this circuit is 0.15 mm2. Measurement results show that the mixer has a 8.4 dB maximum conversion gain, a 3-7 GHz bandwidth, a 13.8-15.8 dB DSB NF within the bandwidth, a 210MHz IF bandwidth, a -0.4 dB IIP3 at 4 GHz, a good port-to-port isolation, and consumes 10.4 mW from a 1.8 V supply.
Finally, the UWB direct-conversion receiver front-end composed of a wideband differential LNA and a wideband passive mixer was implemented in TSMC 0.13 μm CMOS technology. We add a center-tapped inductor which provides differential inductive load with only one coil to extend the bandwidth of the gain, NF and input matching. On the other hand, the capacitive-peaking technique is used in the pre- amplifier of the passive mixer to extend the bandwidth of the overall front-end. Only one coil is used in the whole circuit and the core area of the circuit is 0.22 mm2. The circuit simulated with 21-22 dB conversion gain, 3.7-4.2 dB DSB NF within UWB 3.1-10.6GHz and -15.3 dBm IIP3 at 6.6 GHz. Operating at a 1.8 V supply, this circuit consumes 32.8 mW.

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