電路佈局在積體電路實體設計中是一個非常重要的步驟，現今的電路佈局程序通常包含到了全域佈局,合理化,細節佈局。全域佈局會產生一個已經最佳化某些目標的佈局結果，目標包含像是導線長度,可繞性，時序問題等等。合理化會移除所有的在佈局上元件的重疊且保證元件放在合法的位置上，細節佈局會根據全域佈局的結果在更進一步最佳化目標，像是導線長度。因為不只一個目標會在全域佈局中最佳化，所以在合理化和細部佈局中應該維護全域佈局結果的品質，在這篇論文中，我們提出了一個兩步驟的演算法架構來更進一步的最佳化導線長度並同時利用限制元件的最大移動距離來維護全域佈局結果的品質，在第一個步驟中，我們會有效的去消除由高單位密度所造成的懲罰因素。在第二個步驟中，我們會更進一步減少導線長度同時不去增加在上一個步驟中所消除的懲罰因素，在最後的實驗結果中，我們會展示出我們的細部佈局演算法在不同的最大移動距離限制和佈局目標使用率之下可以得到平均12.33%至15.12%的改進。

Placement is one of the important steps in physical design. Modern placement process involves global placement, legalization, detailed placement.
Global placement generate a placement solution with optimized objectives such as wire-length, routability, timing.
Legalization removes cells overlap and makes sure the cells on the placement site.
Detailed placement (DP) relocates cells to obtain a better placement solution.
Since objectives are optimized in global placement, legalization and detailed placement should not only optimized its objective, but also preserved the global placement solution quality.
In this thesis, we proposed a two-stage detailed placement algorithm for minimizing wire-length, also can preserve the global placement solution quality by constraining the cell displacement.
In the first stage, we can effectively eliminate the penalty caused by high cell density.
In the second stage, we further reduce wire-length without increasing the penalty.
In experiments, we use ICCAD 2013 detailed placement contest [3] benchmarks, the result shows we could improve the global placement results 12.36% - 15.15% on average under different
displacement constraint and target placement density.

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