邏輯加密是一種用於保護積體電路智慧財產權的技術，只有被授權的使用者擁有密碼來解鎖積體電路的正確功能。近期研究者提出了一種基於可滿足性演算法的有效攻擊方法，稱為SAT attack，此方法能夠成功破解加密的電路設計。為了加強邏輯加密，本論文提出了一種基於電路訊號干擾的邏輯加密方法，並且能夠加密於時序電路。我們所提出的加密邏輯閘的新方法可以產生電路訊號干擾，並且能夠使用上升和下降的訊號轉換作為邏輯加密的密碼。實驗結果呈現出，我們所提出的加密邏輯閘的新方法擁有能夠高比例的嵌入IWLS2005基準電路的能力。對於具有8、16和32個位元的密碼的加密，使用我們提出的加密方法的加密設計中，電路面積所產生的成本分別為原始電路的10.68％、12.22％和26.11％，而當我們結合其他的邏輯加密技術時，成本可以大大減少。

Logic encryption is a technique used for intellectual property protection. Only authorized users possess keys to unlock the integrated circuits for correct operations. An effective attacking method based on satisfiability (SAT) algorithm, known as SAT attack, was proposed to decrypt an encrypted design successfully. To strengthen logic encryption, this thesis proposes a glitch-based logic encryption method designed for sequential circuits. The proposed new schemes of key-gates can generate glitches, and use rising and falling transitions as key-inputs for the comprehensive logic encryption. Experimental results show that the proposed glitch key-gate (GK) has high capability to be embedded in a set of IWLS2005 Benchmarks. The cell area overhead in the designs encrypted with GKs are 10.68%, 12.22%, and 26.11% on average for encryptions with 8, 16, and 32 key-inputs, respectively, and the overhead can be reduced substantially when we combine other logic encryption methods with our GKs.

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