在本篇論文，我們提出一個以力平衡原理為基礎的佈局配置器。在I/O pad固定的條件下，我們將分析critical path所得的slack及模組間的繞線長度表示成模組（module）間的拉力，利用靜力平衡的原理計算出每個模組的力平衡位置。之後再進行重疊部分消除並將經過critical path的模組置換成面積大但延遲小的版本以獲得最佳的時間效能。實驗結果顯示我們的佈局配置器可以得到一個合理的結果且能夠縮短繞線的長度。

We propose a timing-driven non-slicing floorplanner based on a modified force-directed method in this study. In deep sub-micron design, timing closure issue becomes more critical than chip area. We extract critical paths from gate-level design to and formulate the timing information as the attractive force between blocks and I/O pads. To obtain a feasible solution, a 3-phase approach is employed. The proposed approach can solve timing closure issue in early physical design phase and produce a feasible floorplanning result. We perform experiments on real cases circuits. Experimental results indicate that our floorplanner reduces wire length and performs well in the test cases.

[1] S. M. Sait and H. Youssef, “VLSI physical design automation – Theory and practice,” IEEE Press, 1995.
[2] H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, “VLSI module placement based on rectangle-packing by the sequence-pair”, Proc. on IEEE/ACM International Conference on Computer Aided Design, pp. 134-141, 1996.
[3] P. N. Guo, C. K. Cheng and T. Yoshimura, “An O-tree representation of non-slicing floorplan and its applications”, Proc. on IEEE/ACM Design Automation Conference, pp. 268-273, 1999.
[4] Y. C. Chang, Y. W. Chang, G. M. Wu and S. W. Wu, “B*-tree: a new representation for non-slicing floorplans”, Proc. on IEEE/ACM Design Automation Conference, pp. 458-463, 2000.
[5] X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C. K. Cheng and J. Gu, “Corner block list: An effective and efficient topological representation of non-slicing floorplan,” Proc. on IEEE/ACM International Conference on Computer Aided Design, pp. 8-12, 2000.
[6] G. Huang, X. Hong, C. Qiao and Y. Cai, “A timing-driven block placer based on sequence pair model,” Proc. on Asia and South Pacific Design Automation Conference, Vol. 1, pp. 249-252, 1999.
[7] S. G. Choi and C. M. Kyung, “A floorplanning algorithm using rectangular Voronoi diagram and force-directed block shaping,” Proc. on IEEE/ACM International Conference on Computer Aided Design, pp. 56-59, 1991.
[8] F. Mo, A. Tabbara and R. K. Brayton, “A force-directed macro-cell placer,” Proc. on IEEE/ACM International Conference on Computer Aided Design, pp. 177-180, 2000.
[9] H. Eisenmann and F. M. Johannes, “Generic global placement and floorplanning,” Proc. on IEEE/ACM Design Automation Conference, pp. 269-274, 1998.
[10] T. S. Tia and C. L. Liu, “A new performance driven macro-cell placement algorithm,” Proc. on European Design Automation Conference, pp. 66-71, 1993.
[11] H. Youssef, S. M. Sait and K. J. Al-Farra, “Timing influenced force directed floorplanning,” Proc. on European Design Automation Conference, pp. 156-161, 1995.
[12] G. Vijayan, “Overlap elimination in floorplans,” Proc. on Fourth CSA/IEEE International Symposium on VLSI Design, pp. 157-162, 1991.
[13] Y. C. Chou and Y. L. Lin, “A performance-driven standard-cell placer based on a modified force-directed algorithm,” Proc. on International Symposium on Physical Design, pp. 24-29, 2001.
[14] W. C. Chen, “A timing-driven slicing floorplanner”, Master Degree thesis, National Tsing Hua University, Department of Computer Science, 1999.
[15] Cadence Design Systems, Inc., “LEF/DEF language reference,” Product Version 5.0, February 1997.