半導體製造流程是相當繁複的，且需要昂貴的原料、精密的機器，在高標準的無塵製造環境中才能生產，使得半導體產業具有高成本、短生命週期的特性，所以如何提升半導體製程的良率，已經成為一門重要的課題。然而由於晶圓表面電路密度的變異，將會降低晶圓表面的平坦程度，故在半導體製程之化學機械研磨時，由於研磨墊加壓於晶圓表面上的應力分布不均造成表面凹陷的品質不良現象，稱之為淺碟效應 (Dish Effect)。本研究之目的為提出一個適用在半導體製造之化學機械研磨階段的平坦化方法，在半導體晶圓電路圖的設計階段時，以考慮在不違反電路設計規則的前提之下，在合理的工程時間要求之內，將龐大的電路圖資料量以有效率的方法，來進行虛擬電路之填充，以降低淺碟效應之影響。

The process of semiconductor fabrication is very complex and expensive materials, precise machines and high-standard environment are required for the entire production. High cost and low life cycle have been two of the characteristics of semiconductor industry. How to enhance yield such that the manufacturing cost can be reduced has become one of the most important issues. Finding out factors that may affect yield and continuing to keep track of these factors in the design phase with production design engineers is a good method to effectively improve yield. The purpose of the Chemical Mechanical Polishing (CMP) process is to planarize heights caused by the deposition of thin films such that further levels may be added onto a flat surface.

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