近幾年，智慧型手機、平板電腦等可攜式電子產品快速發展普及，3C對小體積大容量的儲存裝置需求日漸增加。快閃記憶體(Flash Memory)是目前市場中眾多非揮發性記憶體的主流，然而隨著製程微縮，Flash memory即將面臨到其物理極限，這也加速了許多新型記憶體的研究，其中最被看好的下一世代記憶體為電阻式隨機存取記憶體。
本篇論文提出一種新型雙位元通孔電阻式隨機存取記憶體(Twin-bit Via Resistive Random Access Memory, Twin-bit Via RRAM)，此記憶體通孔兩邊皆有氧化物薄膜，因此單一元件即擁有雙位元儲存。此論文中的研究元件是製作於銅製程雙鑲嵌結構，採用28奈米High-k metal gate互補式金氧半導體邏輯製程，此元件優點為低阻態擁有自我整流特性、極大的高低阻態比、轉換速度快、完全相容於互補式金氧半導體邏輯製程以及優異之可靠度特性。
由於三維快閃記憶體陣列的成功，為了與之競爭，電阻式記憶體勢必也要能堆疊成三維陣列。因為雙位元通孔電阻式記憶體的自我整流特性，在堆疊三維陣列時無需加入額外的整流器；在設計的操作電壓下，此元件陣列通過了10k次設置/重置干擾；此陣列是完全建構在後端製程，周邊電路可以放在陣列的正下方，進一步節省面積。本篇論文提出的雙位元通孔電阻式記憶體及其陣列，有機會成為下一世代記憶體陣列的解決方案之一。

[1] J.C. Slonczewski, “Current-driven excitation of magnetic multilayers”, in J. Magn. Magn. Mater. 159, L1-L7, 1996.

[2] C.J. Lin, S.H. Kang, Y.J. Wang, K. Lee, X. Zhu, W.C. Chen, X. Li, W.N. Hsu,Y.C. Kao, M.T. Liu, W.C. Chen, YiChing Lin, M. Nowak, N. Yu, Luan Tran, ” 45nm Low Power CMOS Logic Compatible Embedded STT MRAM Utilizing a Reverse-Connection 1T/1MTJ Cell”, in IEDM, pp.279-282, 2009.

[3] Bheda, R.A., Poovey, J.A., Beu, J.G., Conte, T.M., “Energy Efficient Phase Change Memory Based Main Memory for Future High Performance Systems” , in Green Computing Conference and Workshops, pp.1-8, 2011.

[4] R. E. Simpson, P. Fons, A. V. Kolobov, T. Fukaya, M. Krbal, T. Yagi, J. Tominaga, “Interfacial phase-change memory”, in Nature nanotechnology, pp.501-505, 2011.

[5] Jaehoon Jang, Han-Soo Kim, Wonseok Cho, Hoosung Cho, Jinho Kim, Sun Il Shim, Younggoan Jang, Jae-Hun Jeong, Byoung-Keun Son, Dong Woo Kim, Kihyun Kim, Jae-Joo Shim, Jin Soo Lim, Kyoung-Hoon Kim, Su Youn Yi, Ju-Young Lim, Dewill Chung, Hui-Chang Moon, Sungmin Hwang, Jong-Wook Lee, Yong-Hoon Son, U-In Chung, Won-Seong Lee, “Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory”, in VLSI Symp. Tech. Dig., pp.192-193, 2009.

[6] H.Tanaka, M.Kido, K.Yahashi, M.Oomura, R.Katsumata, M.Kito, Y.Fukuzumi, M.Sato, Y.Nagata, Y.Matsuoka, Y.Iwata, H.Aochi, A.Nitayama, “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, in VLSI Symp. Tech. Dig., pp.14-15, 2007.

[7] Hong-Yu Chen, Shimeng Yu, Bin Gao, Peng Huang, Jinfeng Kang, H.-S. Philip Wong, “HfOx Based Vertical Resistive Random Access Memory for Cost-Effective 3D Cross-Point Architecture without Cell Selector”, in IEDM, pp.497-500, 2012.
[8] J. F. Gibbons, W. E. Beadle, “Switching properties of thin NIO films”, in Solid-State
Electron, vol.7, no.11, pp.785-790, 1964.

[9] G. Dearnale, A. M. Stoneham, D. V. Morgan, “Electrical phenomena in amorphous oxide films”, in Rep. Prog. Phys., vol.33, pp1129-1191, 1970.

[10] Chin Yu Mei, Wen Chao Shen, Y. –D. Chih, Ya-Chin King, Chrong Jung Lin, “28nm high-k metal gate RRAM with fully compatible CMOS logic processes,” in VLSI-TSA, p.1, 2013.

[11] Y. Watanabe, J. G. Bednorz, A. Bietsch, Ch. Gerber, D. Widmer, A. Beck, and
S. J. Wind, “Current-driven insulator-conductor transition and nonvolatile memory in chromium-doped SrTiO3 single crystals”, in Appl. Phys. Lett., vol.78, pp.3738–3740, 2001.

[12] A. Beck, J. G. Bednorz, C. Gerber, C. Rossel, and D. Widmer, “Reproducible switching effect in thin oxide films for memory applications”, in Appl. Phys. Lett., vol.77, pp.139–141, 2000.

[13] C. Cagli, D. Ielmini, F. Nardi and A. L. Lacaita, “Evidence for threshold switching in the set process of NiO-based RRAM and physical modeling for set, reset, retention and disturb prediction”, in IEDM, pp.1-4, 2008.

[14] Min-Che Hsieh, Yu-Cheng Liao, Yung-Wen Chin, Chen-Hsin Lien, Tzong-Sheng Chang, Yue-Der Chih, Sreedhar Natarajan, Ming-Jinn Tsai, Ya-Chin King , Chrong Jung Lin, “Ultra high density 3D via RRAM in pure 28nm CMOS process”, in IEDM, pp.10.3.1-10.3.4, 2013.

[15] S. Yu, H.-S. Philip Wong, “Compact Modeling of Conducting-Bridge Random-Access Memory (CBRAM),” in TED, pp.1352-1360, 2011.

[16] Ching-Hua Wang, Yi-Hung Tsai, Kai-Chun Lin, Meng-Fan Chang, Ya-Chin King, Chrong Jung Lin, Shyh-Shyuan Sheu, Yu-Sheng Chen, Heng-Yuan Lee, Frederick T. Chen, Ming-Jinn Tsai, “Three-Dimensional 4F2 ReRAM With Vertical BJT Driver by CMOS Logic Compatible Process,” in TED, pp.2466-2472, 2011.

[17] Min-Che Hsieh, Yung-Wen Chin, Yu-Cheng Lin, Yu-Der Chih, Kan-Hsueh Tsai, Ming-Jinn Tsai, Ya-Chin King, and Chrong Jung Lin,” A new laterally conductive bridge random access memory by fully CMOS logic compatible process”, in Jpn. J. Appl. Phys., pp.1-5, 2014.
[18] Z. Fang, H. Y. Yu, X. Li, N. Singh, G. Q. Lo, and D. L. Kwong, “HfOx /TiOx /HfOx /TiOx Multilayer-Based Forming-Free RRAM Devices With Excellent Uniformity”, in EDL, VOL.32, NO.4, pp.566-568, 2011.
[19] Chun-I Hsieh1, Jui-Hsiu Jao, Wei-Chia Chen, Chang-Rong Wu, Neng-Tai Shih, “Forming-free Resistive Switching of TiOx Layers with Oxygen Injection Treatments”, in VLSI-TSA, pp.1-2, 2011.

[20] B. Gao, J. F. Kang, Y. S. Chen, F. F. Zhang, B. Chen, P. Huang, L. F. Liu, X. Y. Liu,
Y. Y. Wang, X. A. Tran, Z. R. Wang, H. Y. Yu, Albert Chin, “Oxide-based RRAM: Unified microscopic principle for both unipolar and bipolar switching”, in IEDM, pp.17.4.1-17.4.4, 2011.

[21] Ching-Hua Wang, Yi-Hung Tsai, Kai-Chun Lin, Meng-Fan Chang, Ya-Chin King, Chrong-Jung Lin, Shyh-Shyuan Sheu, Yu-Sheng Chen, Heng-Yuan Lee, Frederick T. Chen, Ming-Jinn Tsai, “Three-Dimensional 4F2 ReRAM Cell with CMOS Logic Compatible Process”, in IEDM, pp.664-667, 2010.

[22] Ugo Russo, Daniele Ielmini, Carlo Cagli, Andrea L. Lacaita, “Self-Accelerated Thermal Dissolution Model for Reset Programming in Unipolar Resistive-Switching Memory (RRAM) Devices”, in TED, VOL.56, NO.2, pp. 193-200, 2009.

[23] Bin Gao, Bing Sun, Haowei Zhang, Lifeng Liu, Xiaoyan Liu, Ruqi Han, Jinfeng Kang, Bin Yu, “Unified Physical Model of Bipolar Oxide-Based Resistive Switching Memory”, in EDL, VOL.30, NO.12, pp.1326-1328, 2009.

[24] Jinfeng Kang, Bin Gao, Bing Chen, Peng Huang, Feifei Zhang, Lifeng Liu, Xiaoyan Liu, “Physical Mechanism of Resistive Switching and Optimization Design of Cell in Oxide-based RRAM,” in ICSICT, pp.1-4, 2012.

[25] B. Chen, Y. Lu, B. Gao, Y.H. Fu, F.F. Zhang, P. Huang, Y.S. Chen, L.F. Liu, X.Y. Liu, J.F. Kang, Y.Y. Wang, Z. Fang, H.Y. Yu, X. Li, X.P. Wang, N. Singh, G. Q. Lo, D. L. Kwong, “Physical Mechanisms of Endurance Degradation in TMO-RRAM”, in IEDM, pp.12.3.1-12.3.4, 2011.

[26] Myoung-Jae Lee, Youngsoo Park, Bo-Soo Kang, Seung-Eon Ahn, Changbum Lee, Kihwan Kim, Wenxu. Xianyu, G. Stefanovich, Jung-Hyun Lee, Seok-Jae Chung, Yeon -Hee Kim, Chang-Soo Lee, Jong- Bong Park , In-Gyu Baek, In-Kyeong Yoo, “2-stack ID-IR Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications”, in IEDM, pp.771-774, 2007.

[27] Yuan Heng Tseng, Chia-En Huang, C. -H. Kuo2, Y. -D. Chih, Chrong Jung Lin, “High Density and Ultra Small Cell Size of Contact ReRAM (CR-RAM) in 90nm CMOS Logic Technology and Circuits”, in IEDM , pp.1-4, 2009.

[28] Wen Chao Shen, Chin Yu Mei , Y. -D. Chih, Shyh-Shyuan Sheu, Ming-Jinn Tsai, Ya-Chin King, Chrong Jung Lin, “High-K Metal Gate Contact RRAM (CRRAM) in Pure 28nm CMOS Logic Process”, in IEDM, pp.745-748, 2012.

[29] Eike Linn, Roland Rosezin, Carsten Kügeler and RainerWaser, “Complementary resistive switches for passive nanocrossbar memories,” in Nat. Mater., vol.9, no.5, pp.403-406, 2010.

[30] Min-Che Hsieh, Yu-Cheng Liao, Yung-Wen Chi , Chen-Hsin Lien, Tzong-Sheng Chang, Yue-Der Chih3, Sreedhar Natarajan, Ming-Jinn Tsai, Ya-Chin King, Chrong Jung Lin, “Ultra High Density 3D Via RRAM in Pure 28nm CMOS Process”, in IEDM, pp.10.3.1-10.3.4, 2013.

[31] X.A. Tran, B. Gao, J.F. Kang, X. Wu, L. Wu, Z. Fang, Z.R. Wang, K.L. Pey, Y.C. Yeo, A.Y. Du, M. Liu, B.Y. Nguyen, M.F. Li, H.Y. Yu, “Self-Rectifying and Forming-Free Unipolar HfOx based-High Performance RRAM Built by Fab-Avaialbe Materials”, in IEDM, pp.31.2.1-31.2.4, 2011.

[32] H.-S. Philip Wong, Heng-Yuan Lee, Shimeng Yu, Yu-Sheng Chen, Yi Wu, Pang-Shiu Chen, Byoungil Lee, Frederick T. Chen, Ming-Jinn Tsai, “”Metal-Oxide RRAM”, in Proceedings of the IEEE, pp.1951-1970, 2012.

[33] Y. Sasago, M. Kinoshita, T. Morikawa, K. Kurotsuchi, S. Hanzawa, T. Mine, A. Shima, Y. Fujisaki, H. Kume, H. Moriya, N. Takaura and K. Torii, “Cross-point phase change memory with 4F2 cell size driven by low-contact-resistivity poly-Si diode”, in VLSI, pp.24-25, 2009.

[34] I. G. Baek, D. C. Kim, M. J. Lee, H.-J. Kim, E. K. Yim, M. S. Lee, J. E. Lee, S. E. Ahn, S. Seo, J. H. Lee, J. C. Park, Y. K. Cha, S. O. Park, H. S. Kim, I. K. Yoo, U-In Chung, J. T. Moon and B. I. Ryu, “Multi-layer Cross-point Binary Oxide Resistive Memory (OxRRAM) for Post-NAND Storage Application”, in IEDM, pp.750-753, 2005.

[35] G.Tallarida, N.Huby, B. Kutrzeba-Kotowska, S.Spiga, M.Arcari, G.Csaba, P.Lugli, “Low temperature rectifying junctions for crossbar non-volatile memory devices”, in IMW, pp.1-3, 2009.

[36] Jiun-Jia Huang, Yi-Ming Tseng, Wun-Cheng Luo, Chung-Wei Hsu, and Tuo-Hung Hou, “One Selector-One Resistor (1S1R) Crossbar Array for High-density Flexible Memory Applications”, in IEDM, pp.733-736, 2011.

[37] Akifumi Kawahara, Ryotaro Azuma, Yuuichirou Ikeda, Ken Kawai, Yoshikazu Katoh1, Kouhei Tanabe, Toshihiro Nakamura, Yoshihiko Sumimoto, Naoki Yamada, Nobuyuki Nakai, Shoji Sakamoto, Yukio Hayakawa, Kiyotaka Tsuji, Shinichi Yoneda, Atsushi Himeno, Ken-ichi Origasa, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono, “An 8Mb Multi-Layered Cross-Point ReRAM Macro with 443MB/s Write Throughput”, in ISSCC, pp.432-434, 2012.