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研究生: 周學良
Chou, Hsueh-Liang
論文名稱: 整合型高壓金氧半導體元件特性及可靠度退化行為之探討
Investigation on Characteristics and Degradation Behaviors of Integrated High-Voltage MOSFET Transistors
指導教授: 龔正
Gong, Jeng
黃智方
Huang, Chih-Fang
口試委員: 龔正
黃智方
許順良
林恆光
李坤彥
學位類別: 博士
Doctor
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2013
畢業學年度: 101
語文別: 英文
論文頁數: 133
中文關鍵詞: 高壓元件可靠度
外文關鍵詞: High Voltage MOSFET, LDMOSFET, DEMOSFET
相關次數: 點閱:2下載:0
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  • 中文摘要
    積體電路的運算速度藉著CMOS電晶體依循摩爾定律的微縮演進不斷提昇,為了實現更豐富多元性及高效能的設計,高壓元件應用在日益新穎的電子產品中的需求逐漸成長。因此,為了滿足大部分消費性電子設計規格,我們在0.18μm製程上開發了一個高壓功率元件平台(BCD platform),提供介於5V 至 70V之間操作的各種高壓元件。為了降低導通時的功率損耗,特別針對元件的導通電阻加以改善,相較於國際大廠在整合型功率元件所發表的效能,我們所提供的元件在導通電阻上達到15至40%的改善。
    對於特定的應用規格,高壓元件的開發常會採用不同的結構工藝及改善技法,以提供最佳元件效能,尤其是這類的高壓功率元件平台,更要仔細考慮各元件與應用端的聯結。Kirk 效應是高壓元件中常見的現象,通常會改變元件的電場分佈或衝擊游離的產生機制等,間接影響元件特性或可靠度的退化行為,而Kirk效應在不同的電壓條件、漂移區的摻雜狀況或者是結構設計都會出現不一樣的影響結果。因此,研究高壓元件時常會觀察到許多獨特的特徵曲線及可靠度退化機制,這些現象常常迥然不同於傳統的電晶體理論模型。
    本論文將闡述此高壓功率元件平台的設計重點及其優異成果的展示,同時也針對開發過程中所觀察到的非典型元件特性行為進行深入的探討。


    Abstract
    With the evolution of Moore’s law in CMOS technologies, the demands of high-voltage MOSFET transistors (HVMOS) are also rapidly increasing for the diversifications and functionalities in modern electronic product. For the reason, a 0.18μm BCD platform is developed for major consumer applications. This platform consists of modular processes with comprehensive device options in 5V to 70V ratings. To improve the conduction loss, 15~40% reduction of device on-resistance are achieved compared to state-of-art industrial IC-based competitors.
    Due to specific application requirements, various architectures as well as design techniques are introduced to construct the HVMOS in this BCD platform. It is known that the Kirk’s effect usually dominates the electric field distribution and impact-ionization generation. The influence is significant to device characteristics and the reliability degradations but varying with operation voltage, drift region profile, doping concentration and device architecture. Consequently, exceptional device characteristics and hot-carrier-injection (HCI) degradation behaviors are quite prevalent and distinct from the traditional understandings.
    In the dissertation, the design considerations and the achievements of the BCD platform are demonstrated. A few cases with respect to the atypical device characteristics while developing the BCD technology are comprehensively investigated as well.

    中文摘要 i Abstract ii Contents iii Figure Captions v Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Applications of High-Voltage Technologies 2 1.3 Reliability Issues in MOS Devices 3 1.3.1 Low Voltage CMOS Reliability Tests 4 1.3.2 High Voltage Technology Reliability Tests 4 1.4 Organization of this Dissertation 5 Chapter 2 Development, Achievement, and Challenges on HV MOSFET Transistor 11 2.1 Concept of RESURF Technology 13 2.2 Safe-Operating-Area (SOA) 14 2.3 Process Flow of Integrated High Voltage technology 16 2.4 Achievement of High Performance BCD Platform 18 2.5 Atypical Device Characteristics and Reliability Issues 18 Chapter 3 Interpretation of the Current Expansion Phenomenon in n-LDMOS 35 3.1 Introduction 35 3.2 Device Structure 36 3.3 Device Characteristics 37 3.4 Device Characteristics Analysis 39 3.4.1 Output Characteristics at Room Temperature 39 3.4.2 Source Output Characteristics 41 3.4.3 Body Current Characteristics 43 3.5 Conclusion 44 Chapter 4 HCI-Induced Idlin Degradation and Premature GOX Breakdown in HVPAMOS 56 4.1 Introduction 57 4.2 Experimental Details 57 4.2.1 Device Structure and Process Features 57 4.2.2 HCI Stress Setup and Measurement 58 4.3 Result Analysis and Mechanism Discussion 58 4.3.1 Linear Region Drain Current Degradation 60 4.3.2 HCI-Induced Premature GOX Breakdown 61 4.4 Conclusion 63 Chapter 5 Investigation on HCI-Induced atypical Idsat Enhancement in HV Symmetric n-DEMOS 80 5.1 Introduction 81 5.2 Experimental Details 81 5.3 HCI Degradation under Different Stress Conditions 82 5.4 Model and Mechanism Verification 83 5.5 Conclusion 86 Chapter 6 Dimension-Dependence of Unusual Vth Degradation in HV Asymmetric n-DEMOS 102 6.1 Introduction 102 6.2 Experimental Details 104 6.3 Device Characteristics 105 6.3.1 Device Characterization and HCI Degradation 105 6.3.2 Simulation Model 107 6.3.3 Simulation Results and Mechanism Verification 110 6.4 Conclusion 112 Chapter 7 Conclusion and Prospect 126 7.1 Conclusion 126 7.2 Prospect 127 Reference 129

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