由於NOR 型多重邏輯快閃記憶體的寫入，是藉由熱載子傳輸來
達到電荷儲存的目的。因此藉由控制位元線電壓大小，達到多重邏輯
晶片需求更細緻的臨限電壓，運用第一階段步進波形控制加上第二階
段固定電壓的寫入機制，達到四個位階的分佈，能夠座落於正確的目
標，同時考慮寫入時間花費與最佳化的寬度，達到雙贏互利的結果。
針對多重邏輯記憶體元件的電性，調變SONOS 的上氧化層、中氮化
層與下氧化層厚度的實驗設計，分析與改善對臨限電壓、崩潰電壓等
基本電性特徵要求，決定必要的製程參數，適當運用於記憶體上，抑
制二次位元效應，以利元件正常操作。多重邏輯元件的可靠度，藉由
元件本身受干擾的因素以及針對不同烘烤溫度-時間做老化測試，推
估元件的壽命時間與資料儲存能力。選取記憶體元件內部的參考記憶
細胞，做不同汲極電壓與干擾次數的實驗。也對元件主體陣列的記憶
體，施以讀取不同的干擾次數與位元線電壓，觀察其VT 上昇程度。
最後，取得通道寬度為115nm 與90nm 的SONSO 元件，實驗歷經
125℃溫度烘烤於不同的時間，分析各邊界點的視窗邊限位移、Level
讀取電壓位移與左右參考記憶細胞電壓位移，因烘烤後電荷流失之
故，使部份元件的讀取Window 下降而造成判讀錯誤。通道寬度的有
效縮減可抑制上述缺點，使其更有利於Flash 可靠度的提昇。

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