本論文旨在探討如何在不影響線性度的情形下，降低高解析度電流切換式數位類比轉換器之面積與製作成本。我們分別提出兩種方式來改善。第一種方式採用新型的自我校正來補償故意縮小的電流源所導致的電流誤差。兩條閉迴路回授系統能分別偵測及校正平均偏移電流以及其餘的不匹配電流。由於大部分的校正的過程都是利用數位訊號處理，此方法可以容易被應用在其餘高解析度的數位類比轉換器，尤其是在數位電路比類比電路佔有優勢的深次微米世代裡。我們以一個十二位元數位類比轉換器來驗證我們所提出的方法，它採用90nm CMOS製程，核心面積是0.18 mm^2。量測到的DNL及INL分別為0.26 LSB及0.42 LSB。在400-MS/s的操作頻率下，在30MHz的頻寬內能維持59dB以上的無雜訊動態範圍(SFDR)。第二種方式採用動態元件匹配技術(DEM)。傳統的DEM技巧雖然能有效提昇SFDR，但常因需要額外的元件切換而導致嚴重的突波問題。我們提出一個新型的DEM方法來達成最小的元件切換，稱為隨機交換式溫度計編碼技術(Random Swapping Thermometer Coding, RSTC)。它保有了隨機(randomization)及連續選擇(consecutive selection)兩種特性，並且實現電流源的最小切換，使得突波能量可以跟溫度計解碼器的數位類比轉換器一樣小。此外我們也提出了限制跳躍(restricted jumping)的技術來改善低頻諧波的問題。我們將這個方法應用在一個十四位元的數位類比轉換器。採用55nm CMOS製程，此數位類比轉換器的核心面積為0.28 mm^2，電流源僅有相當於十位元的匹配效果。量測結果在100MS/s的操作頻率下，低頻的SFDR可由62dB提升到79dB。

This thesis investigates the techniques to reduce the silicon area of CMOS current-steering digital-to-analog converters (DACs) without compromising the circuit linearity. Conventional high-resolution DACs have to pay a penalty of large-size transistors to get better matching characteristics, thereby increasing the fabrication cost. In this thesis, two methods are proposed to achieve low-cost and high-resolution current-steering DACs.

A self-correction method is developed in the first work. To minimize the area, the transistor size of current source array is reduced deliberately. This shrink will corrupt the DAC linearity performance. With the assistance of a current comparator, a calibration DAC (CalDAC) and calibration logics, two calibration loops are employed to estimate the current mismatches. Since all calibration processes work in the digital domain, the overhead for analog circuit is minimized. In the meanwhile, the proposed methodology can be easily ported to other high-resolution current-steering DACs, especially for deep-submicron processes. We designed a
12-bit video DAC prototype to demonstrate the proposed scheme. Experiment results show the proposed method reduces the DNL and INL to 0.26 and 0.42 LSB, which guarantees 12-bit linearity. At 400-MS/s update rate, the spurious-free dynamic range is above 59 dB within a 30-MHz bandwidth, which corresponds to the signal bandwidth for HDTV applications. This prototype occupies only 0.18mm^2 die area including all calibration functions in a standard 90-
nm CMOS technology.

Besides the calibration, dynamic element matching (DEM) is another effective method to increase the spurious free dynamic range of DACs. The second work describes a new DEM
method called Random Swapping Thermometer Coding (RSTC). The direction selected for a sequence of unit current sources will be randomly changed. Combining this method with the restricted jumping technique the low-frequency idle tones can be mitigated. This approach minimizes the number of switched elements and transient glitches as code changes, while achieving good spectrum purity as other DEM implementations. This method is applied to a 14-bit current-steering DAC with a 4+4+6 double-segmented structure. The first four bits (MSB) and the middle four bits (ULSB) are converted into thermometer codes and employ the proposed RSTC algorithm, which can relax the matching requirement on current cells. The test chip draws 70mW from the supplies with 20mA full-scale current, and occupies only 0.28 mm^2 active area in a standard 55-nm CMOS process. From measurement results of the test chip, it
has been shown to display only 10-bit static linearity with INL around 16LSB. The dynamic performance obtained after applying RSTC algorithm is enhanced from 62dB to 79dB at low
frequencies for a 100MHz sampling clock.

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