本論文主要探討應用於地面/手持式數位影像廣播(DVB-T/H)行動式接收機，其內容包含先前相關研究的研讀，系統模擬與架構設計，以及電路設計和晶片實現。

許多關於接收的研究已經被討論過包括同步、載波頻率漂移、取樣頻率偏移。基於這些經過充分研究的接收方法，本論文提出了一個具有低複雜度及高效能的行動接機。本接收機最主要的是行動式等化器。接收機主要是使用一個二階回歸內插器 (Second Order Regression Interpolator)。主要的構想是依據已得到的通道資訊找出一條二次曲線。這個內插器可以分成兩部份，一個是曲線係數的取得，另一個是通道響應的產生。為了增加通道的可靠性，把舊的通道資訊用線性延伸 (Linear Extension) 的方法得新的通道響應。

本論文中，系統模擬建立在F1和P1的靜態通道，還有TU6的行動通道加上加成性白高斯雜訊模型。TU6行動通道是依照Jakes頻譜而產生的。模擬進行在靜態還有動態的通道中。

為了簡化電路面積消耗，快速傳利葉轉換 (Fast Fourier Transform) 採用混合基數的架構，而主要的基數為16。電路採用暫存器交換層級語言描述 (RTL) ，並經由場效可程式閘陣列 (FPGA) 的積體電路設計流程完成設計，最後使用Xilinx Virtex XC4VLX60來實現設計。本電路操作頻率一般為36.57 MHz，此電路支援2k、4k、8k點的快速傳利葉轉換。

在電路實現後，一些增強接收機的功能也被提出，例如內部載波相互干擾的降低和硬體共用，這些技術提供了在未來實現一個更優秀地面/手持式數位廣播接收機的契機。

In this thesis, standard specification study, functional simulation, architecture design and circuit design along with FPGA implementation of multiple-point FFT, multiple constellations, and multiple guard interval ratio is presented.

Several receiving techniques are discussed, including synchronization, CFO compensation, and SFO compensation. Based on these receiving techniques, a mobile receiver architecture with low complexity and high performance is proposed. The key point of proposed receiver is the mobile equalizer. The proposed equalizer architecture is implemented by a second order regression interpolater. The key idea is to find a quadratic curve according to the channel information now. This interpolater is divided into two parts called the acquisition of interpolation coefficients and the channel response generation. To enhance the reliability of channel information, the new channel response is predicted by linear extension of old channel information.

Simulations are based on the F1 channel, P1 channel, and mobile TU6 channel with white noise. The mobile TU6 channel is based on the Jakes Doppler spectrum. Simulations are under static channels and dynamic channels.

To minimum the area of the proposed receiver, the FFT is implemented in mixed-radix based on 16-point FFT. The proposed receiver is implemented with synthesizable Verilog RTL codes by FPGA design flow. The receiver is implemented in Xilinx Virtex4 XC4VLX60. The clock operates at 36.57 MHz normally. This circuit can support 2k-, 4k-, and 8k-point FFT.

After implementation of the circuit, several enhancements are also proposed such as ICI cancelation and hardware sharing. These provide the direction to implement a more
excellent DVB-T/H receiver in the future.

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