在下一代通訊系統中，隨著人們對於快速以及高品質資料傳輸的要求與日俱增，高速渦輪解碼器的設計成為一個非常重要的研究領域。在本論文中，我們設計了一個適用於3GPP-LTE可變動區塊大小的高速渦輪解碼器。針對解碼速度方面，我們採用了平行區塊處理技術與radix-16最大事後機率演算法來提升平行度。此外，字元長度縮減化(word length shortening)的技術也被用來降低運算複雜度，此技術將同時改善面積以及電路延遲。另一方面，我們也設計出指令式交互連接器來提升對於不同區塊大小的支援性。同時針對於高平行度所面臨到的記憶體衝突問題，我們也提出無衝突導向的記憶體重置演算法來產生適當的指令組合以搭配交互連結器的運作。透過此重置演算法，所設計出來的渦輪解碼器將可在平行度高於 16 的情況下運行。最後，我們將所設計的radix-16 MAP處理器利用90nm UMC COMS製程與Faraday cell library以單晶片的方式實現；而渦輪解碼器則是搭配上一組 radix-16 MAP處理器並實現在FPGA模組上。透過完整的驗證流程後，所設計的MAP處理器將達到571Mb/s 的傳輸速率，而使用相同製程所合成的渦輪解碼器將在8次迭代的環境下達到35.24Mb/s的傳輸速率，其能量效能為 0.14nJ/b/iter。

Since the next-generation wireless communication systems target to achieve high data rate and high transmission reliability, research on design and implementation of the channel codec becomes a challenging issue. The Turbo code is one of the most popular channel coding schemes for digital communication systems.

In this thesis, a high-throughput Turbo decoder for 3GPP-LTE system is proposed. Both the parallel sub-block processing and radix-16 modified Log-MAP algorithm are used to minimize the performance loss, and the word length shortening technique is proposed to reduce the complexity. Besides, the supportability of variable block size is also accomplished by the proposed instruction-based interconnection circuits with instruction ROM. The instructions are pre-processed by the proposed contention-free oriented memory remapping algorithm. Related to the parallelism degree, the proposed remapping algorithm enables the contention-free feasibility with parallelism degree larger than 16, which is larger than that of the QPP interleaver in 3GPP-LTE Turbo decoding.

The radix-16 reduced complexity MAP processor is designed and implemented as a single chip, and the proposed variable-block-size Turbo decoder with one raidx-16 MAP processor is realized as a prototype on FPGA module. The well-verified chip using 90nm UMC CMOS technology and Faraday cell library can achieve 571 Mb/s data rate with 392k gate counts. Moreover, the Turbo decoder is also synthesized with the same design kit. It has the throughput of 35.24Mb/s with 8 iterations, and the energy efficiency of this decoder is 0.14 nJ/b/iter.

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