近年來由於元件操作電壓隨著製程的演進而逐漸降低，因而導致CMOS APS的輸出範圍(Output Swing)以及訊雜比(Signal to Noise Ratio, SNR)也跟著逐漸縮小，因而增加了後段類比數位轉換器（ADC）電路設計上的困難。因此，近年來將類比數位轉換器做在每一個像素內的數位像素感測器（Digital Pixel Sensor, DPS）的研發已經成為一種趨勢。由於每一個像素的輸出已經是數位訊號，因此，低的輸出範圍以及行與行之間的讀出雜訊(readout noise)對於像素特性的影響將會大大的降低。但是較大的像素面積是數位像素感測器的最大缺點，這將限制數位像素感測器在高解析度影像感測器上的應用。
本篇論文提出的第一個架構是一個時脈(clock)輸出的數位像素感測器，而它每一像素只需要十個電晶體。這個新的像素的輸出特性類似於一個放大的對數輸出響應，這樣的輸出特性和人的眼睛對光的響應非常的類似。此外這個像素的比較器輸入補偏電壓(input offset voltage)的問題，也可以經由特殊的操作來解決。且這個新像素的動態範圍，經由模擬結果得知可以輕易的大於90dB。然而功率消耗太大以及操作速度太慢都是它的問題，因而會限制它的應用範圍。
而本篇論文所提出的第二個新的架構，每一個像素包含有一個位元的記憶體，因此他每一個像素需要十五個電晶體。雖然這個像素比前一個像素多了五個電晶體，但他卻完全的擁有第一個像素的優點，然而第一像素的缺點操作速度太慢以及功率消耗太大都可以獲得有效的改善。由於這個數位像素感測器的操作是一次讀出一個位元，因而我們可以利用這個特性實現影像的邊緣偵測應用，進而更可以偵測整個影像感測器陣列是否有壞點。

Abstract

Digital pixel sensor (DPS) which includes an A/D converter in each pixel has been developed in the past few years. With pixel level A/D conversion, higher SNR can be achieved, and the small output voltage swing has less impact on imaging quality. Furthermore, by employing A/D converter and memory at each pixel, high speed digital readout can be achieved and therefore provide more rooms for aggressive image-processing applications. Studies adapting multiple imaging capturing or synchronous self-reset schemes were proposed for widening the dynamic range of a linear response pixel. Even though, large pixel area is still the main drawback for most digital pixel sensors, and the massively data processing units required to extend dynamic range increases the complexity of periphery circuits and consumes more dynamic power.
In this dissertation, we first presented a clock count output digital pixel sensor which requires only 10 transistors per pixel. The pixel is the clock count output, and is named the CPS. An amplified logarithmic output response similar to the response to light of the human eye is demonstrated by this pixel. The self-offset cancellation scheme of the CPS substantially reduces the FPN caused by the comparator offset drops to less than 2LSB. Moreover, from the estimated results, the dynamic range of the CPS is at 96dB with an 8-bit ADC resolution. Although the CPS can provide a lower supply voltage and a higher dynamic range, the dynamic power consumption and readout speed severely limit the CPS to be applied to high resolution imagers.
To improve the dynamic power and readout speed issues, a new architecture of the bit-frame digital pixel sensor is presented. This holds the benefits of the CPS, such as non-linear transfer curve in one time sampling and its dynamic range, which are also proportional to the ADC resolution. The pixel requires 15 transistors per pixel. The readout speed of this pixel is significantly increased and consumes very low power. Moreover, due to its unique characteristics, a simple manner of detecting the object edges of an image is proposed. By applying this edge detection manner, the self-calibration of faulty pixels can also be implemented.

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