適用於多重輸入輸出行動寬頻無線網路通訊系統之基頻測試平台

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研究生：	吳昱臻 Wu, Yu-Jen
論文名稱：	適用於多重輸入輸出行動寬頻無線網路通訊系統之基頻測試平台 A Baseband Testbed for Mobile MIMO WiMAX Communications
指導教授：	馬席彬 Ma, Hsi-Pin
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	85
中文關鍵詞：	系統晶片設計、驗證、基頻、通訊、嵌入式
外文關鍵詞：	soc, fpga, wimax, wireless, ofdm, ofdma, testbed, baseband, arm
相關次數：	點閱：3 下載：0
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在本篇論文中，主要是呈現一高效率且具彈性化之基頻驗證平台，此一驗證平台整合了其他數位矽智財核心，適用於IEEE 802.16e通訊標準之多重輸入輸出行動寬頻無線網路通訊系統，本基頻驗證平台主要由軟/硬體設計和系統晶片平台所組成，本基頻驗證平台支援上行/下行通訊系統並將其整合於系統晶片平台上，在本基頻驗證平台中，軟體與硬體設計皆已經過合成與驗證，在本研究中提供了完整的系統設計，在開發初期，本基頻驗證平台先以上行系統作為整合目標，而藉由更改其輸入/輸出控制單元，本基頻驗證平台同樣可與下行系統做整合，在本研究中提出的基頻驗證平台提供了具彈性化的開發原型，此一開發原型適用於寬頻無線網路通訊系統。

而為了有效率的處理在每一個不同階段的設計複雜度與設計時間的不足，設計者可採用以系統晶片平台為基礎之系統設計的策略，更進一步，系統晶片設計能有效的降低驗證的不確定性，進而大大得降低設計的風險，而在驗證階段，設計者可以採用軟硬體協同驗證的方法對硬體單元作驗證與除錯，此一驗證流程能幫助設計者以更快的速度完成驗證，而在本驗證平台中，採用圖片檔案作為傳輸媒介，跟傳統驗證流程是以觀察錯誤率/訊雜比趨勢圖，藉以分析系統效能的好壞相比，在本基頻驗證平台中，藉由系統晶片平台上的LCD螢幕，設計者可以直接在螢幕上看到在不同的通道環境中接收端解出來的結果，由觀察圖片的清晰與否判斷系統效能好壞，更能使設計者有更直接的感受，以達到快速驗證之成果。

In this thesis, an efficient and flexible testbed integrated with intellectual property (IP) cores for multi-input multi-output orthogonal frequency division multiple access (MIMO-OFDMA) transceiver of IEEE802.16e standard is presented. The proposed testbed consist of hardware design, software design and system-on-chip (SoC) platform. The proposed testbed supports uplink/downlink system and integrates those system with SoC platform. The hardware and software design have been synthesized and verified. The proposed testbed provides a complete system design.In the begging of development, the proposed testbed is integrated with uplink system. Through changing input/output control unit and software design, the proposed testbed could apply to downlink system. It is a flexible prototyping for worldwide interoperability for microwave access (WiMAX) communication system.

Designers could use platform-based design approach as an effective strategy to cope with product complexity and time-to-market at all levels. Moreover, SoC design methodology will minimize verification uncertainties that greatly reduce design effort and risk. For the verification stage, designers can use the hardware/software (HW/SW) co-verification strategy to debug hardware component, which will help designers identify more faster. In this proposed testbed, which introduces the figure file to be the transmission media. Designers validate their design in bit error rate/signal-to-noise ratio (BER/SNR) waveforms traditionally. In this proposed testbed, designer could verify the decoded results in various environment by liquid crystal display (LCD) panel.

Introduction 1
1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Introduction of WiMAX System . . . . . . . . . . . . . . . . . . . . 1
1.2 SoC Design Methodology . . . . . . . . . . . . . . . . . . . . . . . 2
2 Motivation of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
System Descriptions 5
1 OFDM and OFDMA System . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 MIMO System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Introduction of IEEE 802.16e Standard . . . . . . . . . . . . . . . . . . . . . 8
3.1 Symbol Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 System Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Uplink System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Downlink System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SoC Platform Architecture 13
1 ARM RISC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 AMBA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 AMBA AHB Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 AMBA APB Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Testbed Architecture for Uplink/Downlink System 23
1 Uplink Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.1 Mapping and Pilot Generation . . . . . . . . . . . . . . . . . . . . . 24
1.2 Data/Pilot Subcarrier Allocation . . . . . . . . . . . . . . . . . . . . 25
1.3 Subchannel Assignment . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4 Inverse Fast Fourier Transform . . . . . . . . . . . . . . . . . . . . . 30
1.5 CP Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2 Uplink Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.1 FFT Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2 Memory Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3 ICI Canceler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.4 MIMO Channel Estimator . . . . . . . . . . . . . . . . . . . . . . . 36
3 I/O Control Unit for Uplink System . . . . . . . . . . . . . . . . . . . . . . 37
3.1 Input Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2 Output Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4 Downlink Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5 I/O Control Unit for Downlink System . . . . . . . . . . . . . . . . . . . . . 41
5.1 Input Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2 Output Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SoC Integration, Verification and Emulation Results 45
1 Integration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2 Uplink System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.1 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . 46
2.2 Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . 48
2.3 Clock Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3 Uplink System Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.1 RTL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2 FPGA Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3 Software Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4 HW/SW Co-verification . . . . . . . . . . . . . . . . . . . . . . . . 54
4 Uplink System Emulation Results . . . . . . . . . . . . . . . . . . . . . . . 54
4.1 Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5 Downlink System Verification . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.1 FPGA Emulation and Software Verification . . . . . . . . . . . . . . 59
5.2 HW/SW Co-verification . . . . . . . . . . . . . . . . . . . . . . . . 59
6 Downlink System Emulation Results . . . . . . . . . . . . . . . . . . . . . . 60
6.1 Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Platform-to-Platform Transmission 65
1 Integration and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1.1 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . 65
1.2 RTL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
1.3 FPGA Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
1.4 HW/SW Co-verification . . . . . . . . . . . . . . . . . . . . . . . . 72
2 Emulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.1 Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Conclusions and Future Works 81
1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

                                

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