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研究生: 吳文彥
Wu, Wen-Yen
論文名稱: 嵌入式數位訊號處理器之記憶體子系統的分析與最佳化
Analysis and Optimization of the Memory Subsystem with Embedded DSP Core
指導教授: 吳仁銘
Wu, Jen-Ming
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2009
畢業學年度: 97
語文別: 英文
論文頁數: 38
中文關鍵詞: 數位訊號處理器記憶體子系統嵌入式最佳化
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  • 海星(starfish)計畫是由國立清華大學與國立交通大學共同開發的計畫。在這個計畫當中,由Platform團隊所開發的子系統包括了幾個元件,分別是直接記憶以存取單元、進階微控制器匯流排架構(AMBA)介面、頁面控制單元、內部緩衝區、追蹤除錯單元以及由RTL團隊所開發的數位訊號處理器(DSP)核心-Starfish。
    然而,由於內部緩衝區有太多的失誤率與失誤處罰時間,導致數位訊號處理器核心之子系統仍然存在很多不必要的執行時間。因此,本篇論文最主要的目的就在於如何減少失誤率與失誤處罰時間,來達到改善數位訊號處理器核心之子系統的效能。本篇論文主要的貢獻在於以下幾項:修改頁面控制單元的錯誤、改變指令緩衝區的頁面替換策略、改變內部緩衝區的頁面配置以及提出預先存取演算法。經由H.264程式的模擬結果,顯示整體子系統在失誤率、失誤處罰時間以及效能上有非常明顯的改善。改變頁面替換策略以及改變頁面配置此兩方法,在RTL模擬的結果中,可以得到最高將近百分之九十七點六的改進,而預先存取演算法也能夠得到最高將近百分之二十的改進。除此之外,我們還使用了多媒體平台(UMVP-2000)來做硬體的驗證。透過此平台的實驗所得到的結果,我們可以驗證RTL模擬所得到的結論是正確的。
    最後,研究結果顯示,我們能夠成功的提升了數位訊號處理器核心之子系統的效能。


    The Starfish project is developed by National Tsing-Hua University and National Chiao-Tung University. In this project, the Starfish Subsystem is designed by the platform team with several components, including DMA (Direct Memory Access), standard AMBA (Advanced Micro-controller Bus Architecture) interface, Page Control Unit, Trace/Debug Unit, internal buffer and the Starfish DSP (Digital Signal Processer) Core that developed from the RTL team.
    However, the overhead of Starfish Subsystem is still high. This is due to the excessive miss rate and miss penalty. Therefore, the aim of this article attempts to explore how to reduce miss rate and miss penalty. The contribution of this thesis are resolved the bug of Page Control Block, proposed page replacement policy of instruction buffer, proposed page configuration of internal buffer and proposed pre-fetch algorithm.
    After RTL simulation with H.264 application, results of simulation shown the overhead of Starfish Subsystem has a lot of reduction. By proposed page replacement policy and page configuration, we can achieve maximum of approximately 97.6% improvement in RTL simulation. By the pre-fetch algorithm, it can provide approximately 20% improvement in RTL simulation. In addition, we use the UMVP-2000 multimedia platform to do hardware verification with H.264 application. The platform experimental results on this platform are confirmed the result of RTL simulation.
    To conclude, results of this study shown a significant improvement in the overhead of Starfish Subsystem.

    Chapter 1 Introduction 1.1 Introduction of Starfish Project 1.2 The Rest of this Thesis Chapter 2 Background 2.1 Starfish Subsystem 2.1.1 AMBA Interface (a) Control Logic (b) External memory (c) Internal Buffer 2.1.2 Page Control Block 2.1.3 Integrated DMA (a) Config-DMA module (b) DMA module 2.2 Library Function 2.3 Simulation Environment 2.4 UMVP-2000 Platform 2.4.1 Features 2.4.2 Working on the UMVP-2000 platform (a) Hardware (b) Firmware(Software) Chapter 3 Analysis of Starfish Subsystem 3.1 The Overhead of Miss in Original Page Control Block 3.2 Page Replacement Policy of Instruction Buffer 3.3 Page Configuration of Internal Buffer 3.4 The Feature of Page Control Block 3.5 Resolved the bug of Page Control Block Chapter 4 Proposed Starfish Subsystem 4.1 Proposed Page Replacement Policy of Instruction Buffer 4.2 Proposed Page Configuration of Internal Buffer 4.2.1 Page Configuration of Instruction Buffer 4.2.2 Page Configuration of Data Buffer 4.3 Proposed Pre-fetch Algorithm 4.3.1 The Principle of Pre-fetch Algorithm 4.3.2 Proposed Pre-fetch Module (a) Swapping a page into data buffer when system bus idles (b) Ensure page that pre-fetching into data buffer will be used soon Chapter 5 Experiment Results and Comparison 5.1 Performance of Proposed Replacement Policy and Page Configuration 5.2 Performance of Proposed Pre-fetch Algorithm 5.2.1 RTL Simulation Result 5.2.2 Platform Simulation Result Chapter 6 Conclusion and Future work Bibliography

    [1] NTHU Design Technology Center, Starfish Development and Implementation, July 2007
    [2] M. C. Hsieh and, C. T. Huang, “Design of the Debugging Infrastructure for the Embedded DSP Core “, October 2007
    [3] Inc. ARM Components, AMBA Specification Rev2.0, May 1999.
    [4] Global UniChip Corp, Users Manual of UMVP-2000 Development Board 0.5.0, Mar. 2005.
    [5] Inc. ARM Components, ARM926EJ-S Development Chip Reference Manual, 2006.
    [6] Global UniChip Corp, UMVP-2000 Multimedia Platform User Manual of FPGA 0.6.2, February 2006.
    [7] Global UniChip Corp, UMVP-2000 Library User Manual 1.0.0, Mar. 2006.
    [8] Altera Corporation, Stratix II Device Family Data Sheet, 2007.
    [9] Inc. ARM Components, RealView Developer v2.2 Suite-Getting Started Guide, 2005.
    [10] Inc. ARM Components, RealView Developer Suite-AXD and armsd Debuggers Guide, 2004.
    [11] Inc. ARM Components, Multi-ICE version 2.2 User Guide, 2002
    [12] Altera Corporation, Staratix II FPGA Family, 2006
    [13] Chih-Da Chien, Chih-Wei Wang, Chuan-Chau Lin, Tien-Wei Hsieh, Yuan-Hwa Chu, and Jiun-In Guo, “A Low Latency Memory Controller for Video Coding Systems,” Proc. 2007 IEEE International Conference on Multimedia & Expo, July 2-5, Beijing, China 2007.
    [14] Kleen, A., Stienberg, E., Anschel, M., Sibony, Y. and Greenberg, S.” An improved instruction cache replacement algorithm”, Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on 2-4 Nov. 2005 Page(s):573 - 578

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