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研究生: 羅士健
論文名稱: 以自適應共振理論網路II建構半導體研發階段黃金晶方粒子群聚分析
Using Adaptive Resonance Theory Network II to Analyze Golden Die Clustering Model at R&D Stage in Semiconductor Manufacturing
指導教授: 洪一峯
劉淑範
口試委員: 陳飛龍
劉淑範
洪一峯
學位類別: 碩士
Master
系所名稱: 工學院 - 工業工程與工程管理學系
Department of Industrial Engineering and Engineering Management
論文出版年: 2011
畢業學年度: 99
語文別: 中文
論文頁數: 76
中文關鍵詞: 半導體晶圓允收測試因素分析自適應共振理論網路II
外文關鍵詞: Semiconductor, Wafer Acceptance Test, Factor Analysis, Adaptive Resonance Theory Network II
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  • 半導體產業在台灣製造業扮演一舉足輕重的角色,在半導體研發過程中,半導體製程工程師會利用測試載具(Test Vehicle)來取得晶圓上晶方的電性參數,取得WAT資料後,半導體工程師將可進一步研究晶方的電性參數,進而找出符合當初設計的最佳晶方及最佳晶方參數。傳統尋找黃金晶方的過程中會遇到幾個問題,一是WAT電性參數資料龐大,二是通常一批晶方參數可能有上百顆晶方,在上百顆晶方中,每顆晶方內含三四百筆電性參數。如此龐大的資料量,對於半導體工程師從中尋找黃金晶方,是一大考驗。有鑑於此,本研究建構一系統性的方法,以工程師最初定義的黃金晶方為基礎,首先利用因素分析將WAT資料維度縮減後,再透過類神經網路中自適應共振理論網路II將資料維度縮減過後的晶方做分群。如此便可快速的找出黃金晶方所屬的類黃金晶方群,可縮減研發製程所需時間以及加快產品上市時間。本研究以竹科某半導體廠之研發階段WAT參數做為實驗數據,並建構一模型將晶方分群,如此可有效且快速找出類黃金晶方。經實驗證實,本研究所提出之分析方法,可有效的輔助半導體工程師尋找類黃金晶方,減少研發階段的耗時。


    Semiconductor industry has played a prominent role in Taiwan manufacturing industry. In the semiconductor research and design stage, the semiconductor engineers would use test vehicle to retain the wafer acceptance test data(WAT) from the wafer, then the semiconductor engineers could find a best die by checking the WAT data. But there are some problems to find the best die by traditional ways, the first problem is that the amount of WAT data is quiet big, the second problem is that there are hundreds of dies in a batch of wafer. It’s really a big test for semiconductor engineers to find the best dies (golden dies) from such a large WAT data. Accordingly, this research aims to build a system model to analyze the WAT data at R&D stage basing on the golden dies which semiconductor engineers defined earlier to help semiconductor engineers find the golden dies. At first step, this research use factor analysis to reduce the WAT data amount. The second step, this research use Adaptive Resonance Theory Network II (ART-2) to cluster the wafer dies. Real WAT data during semiconductor fortification are collected from a semiconductor manufacturing company and were experimented through the presented analysis model. Therefore, the proposed methodology in this research can help the semiconductor engineer find the golden dies more quickly and efficiently, and the analysis time can be reduced during semiconductor fortification.

    摘要 I ABSTRACT II 致謝詞 III 目錄 IV 圖目錄 VII 表目錄 IXX 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機 2 1.3 研究目的 3 1.4 研究架構 4 第二章 文獻探討 6 2.1 半導體相關製程介紹 6 2.2 晶圓允收測試 16 2.3 資料前處理技術 17 2.3.1 特徵選取(Feature Selection) 19 2.3.2 特徵萃取(Feature Extraction) 20 2.3.3 因素分析(Factor Analysis) 22 2.4 資料探勘 22 2.4.1 資料探勘技術介紹 24 2.4.2 類神經網路 26 2.5 半導體抽樣分析介紹 29 第三章 半導體研發階段WAT參數之抽樣分析 31 3.1 問題定義 31 3.2以ART-2建構黃金晶方分群模型 35 3.2.1 資料前處理 37 3.2.2自適應共振理論網路II分群分析 42 第四章 系統實作與實證分析 49 4.1 資料分析 49 4.2 ART-2分群結果分析 57 第五章 結論 68 5.1 結論 68 5.2 未來研究方向 70 參考文獻 71

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