探討生醫晶片中整合類比數位電路在同一個基底上時，雜訊經由基底傳播到晶片各處影響類比電路的特性，這些隱藏的現象在現今電路模擬中並無包含基底特性的資訊，故一般在佈局前模擬電路時都無法了解雜訊經由基底耦合至類比電路的基底端所造成特性的變化，本篇論文首先設計量測基底資訊，建構各種距離下耦合路徑的等效電阻模型，並利用此等效電阻模型依晶片佈局實際情況建構基底耦合路徑加入佈局前模擬，耦合路徑電阻放至在雜訊產生基底接點和類比電路基底端中間當作橋梁連接，彌補電路模型中對於基底描述不足的地方做佈局前模擬，了解晶片系統受基底雜訊影響的程度。
文獻在建構基底耦合路徑模型之後，為了瞭解模型是否準確可預測，都會採用佈局前模擬和量測類比電路特性比較，這是工程常用的方式，畢竟要模型真正反應基底複雜的現象且沒有誤差的預測是困難的，只需達到可接受誤差底下的現象即可。論文中基底耦合路徑模型採用的是巨觀電阻，測試此模型的電路是漸進式逼近類比數位轉換器，除了此電路可廣泛應用在生醫晶片系統中，最主要的原因在於類比數位轉換器有完整的量測分析方法，觀察雜訊影響電路特性變化可以量化表示，例如SNDR、ENOB的變化。
本篇論文的特色在於採用的測試電路為漸進式逼近類比數位轉換器，利用各種波型訊號經由基底傳播路徑干擾取樣保持電路，實際晶片量測和電路模擬比較干擾訊號對於電路特性的影響，量化基底受不同形式訊號干擾時對於整體類比數位轉換器特性的變化，參考的文獻尚未提出此種討論方式，實驗設計的方式不同於文獻提出利用放大器作為測試電路，只單純利用肉眼觀察電路模擬頻譜未受影響和受影響的變化，而可很精準量化類比數位轉換器特性下降的幅度。

Analog and digital circuits are combined on the same substrate of the bio-chip. Noise propagating through the substrate influences analog circuit performances. It is difficult to understand this phenomenon before layout extraction because the technology file which is used to simulate circuits does not include the substrate information. In this thesis, a method to measure the substrate information is designed, and a substrate resistance formula based on the measured substrate information is built. A substrate resistive network is built using the substrate resistance formula according the layout, and the network is added between the noise input and analog circuit for pre-layout simulation to compensate the lack of the technology file.
Once the network is built, simulation results of the circuit with the substrate resistive network before layout extraction are compared to the chip measurement results to study how valid the substrate resistive network is because it is exceedingly difficult to build the perfect substrate resistive network. The Successive Approxi- mation Register Analog to Digital converter (SAR A/D) is used to test the accuracy of the substrate resistance network because SAR A/D is widely applied to bio-chips and complete analysis methods of the SAR A/D such as SNDR and ENOB are available
This thesis’s feature is testing substrate resistive network with the SAR A/D which is different from the testing circuits of references. Using the SNDR and ENOB analysis to quantize circuit variations caused by the noise interference for circuit pre-layout simulation and chip measurement can exactly describe the effect of signal interference. Various types of signals that interfere with the Sample and Hold (S/H) circuit of the SAR A/D are injected into the substrate near the S/H circuit for pre-layout simulation and chip measurement to investigate whether the substrate resistive network accurately represents the substrate coupling paths.

[1]Hsin Chen; Fleury, P.C.D.; Murray, A.F., "Continuous-valued probabilistic behavior in a VLSI generative model," IEEE Transactions on Neural Networks, vol.17, no.3, pp.755-770, May 2006.
[2]Lu, C.C.; Hong, C.Y.; Chen, H., "A Scalable and Programmable Architecture for the Continuous Restricted Boltzmann Machine in VLSI,", IEEE International Symposium on Circuits and Systems, pp.1297-1300, 27-30 May 2007.
[3]Heer, F.; Hafizovic, S.; Ugniwenko, T.; Frey, U.; Roscic, B.; Blau, A.; Hierlemann, A., "Using microelectronics technology to communicate with living cells," IEEE Engineering in Medicine and Biology Society, pp.6081-6084, 22-26 Aug. 2007.
[4]Valorge, O.; Andrei, C.; Calmon, F.; Verdier, J.; Gontrand, C.; Dautriche, P., "A Simple Way for Substrate Noise Modeling in Mixed-Signal ICs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol.53, no.10, pp.2167-2177, Oct. 2006.
[5]SubstrateStorm-SNA Cadence Design Systems, San Jose, CA, 2005 [Online] Available: http://www.cadence.com
[6]R. Gharpurey and R. G. Meher, “Modeling and analysis of substrate coupling in integrated circuits,” IEEE Journal of Solid-State Circuits, vol. 31, pp. 344-353, Mar. 1996.
[7]B. R. Stanisic, N. K. Verghese, L. R. Carley, and D. J. Allstot, “Addressing substrate coupling in mixed-mode IC’s: Simulation and power distribution synthesis,” IEEE Journal of Solid-State Circuits, vol. 29, no. 3, pp. 226-238, Mar. 1994.
[8]A. Samavedam, K. Mayaram, and T. Fiez, “A scalable substrate noise coupling mode for mixed-signal IC’s,” IEEE Transactions on Solid-State Circuits, vol. 35, pp. 895-904, June 2000.
[9]TMA MEDICI Two-dimensional device simulation program, Version3.3, Tech-nology Modeling Associates, Inc., Palo Alto, CA, Feb. 1997.
[10]D. K. Su, M. J. Loinaz, S. Masui and B. A. Wooley, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,” IEEE Journal of Solid State Circuits, vol. 28, pp. 420-429, Apr. 1993.
[11]C.-S. Lin and B.-D. Liu, “A new successive approximation architecture for low-power low-cost CMOS A/D converter,” IEEE Journal of Solid-state Circuits. vol. 38, no. 1, pp. 54-62, Jan. 2003.
[12]R. E. Suarez, P. R. Gray, and D. A. Hodges, “All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques-Part II,” IEEE Journal of Solid-State Circuits, vol. 10, no. 6, pp. 379-385, Dec. 1975.
[13]D. Aksin, M. Al-Shyoukh, and F. Maloberti, “Switch Bootstrapping for Precise Sampling Beyoud Supply Voltage”, IEEE Journal of Solid State Circuits, vol. 41, no. 8, pp. 1938-1943, Aug. 2006.
[14]Aksin, D.; Al-Shyoukh, M.; Maloberti, F., "Switch Bootstrapping for Precise Sampling Beyond Supply Voltage," IEEE Journal of Solid-State Circuits, vol.41, no.8, pp.1938-1943, Aug. 2006.
[15]H.-C. Hong, G.-M. Lee, “A 65-fJ/conversion-step 0.9-V 200KS/s rail-to-rail 8-bit successive-approximation ADC,” IEEE Journal of Solid-State Circuits, vol. 42, no. 10, pp. 2161-2168, Oct. 2007.
[16]J. Steenagaard, “Bootstrapped low-voltage analog switches,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 29-32, 1999.
[17]Chi-Chang Lu and Tsung-Sum Lee, “A 10-bit 60-MS/s Low-Power CMOS Pipelined Analog-to-Digital Converter”, IEEE Transactions on Circuits and Systems, vol. 54, no. 8, August 2007.
[18]P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. Oxford, U.K.: Oxford Univ. Press, 2002.
[19]A. Rossi and G. Fucilli, “Nonredundant successive approximation register for A/D converters,” Electron. Lett., vol. 32, no. 12, pp. 1055-1057, June 1996.
[20]D. Khalil, M. Dessouky, V. Bourget, M.-M. Louerat, A. Cathelin, and H. Ragai, “Compensated layout for automated accurate common-centroid capacitor arrays,” IEEE ICEEC Dig. Tech. Papers, pp. 481-484, 2004.