在本論文中,我們針對數位訊號處理器,研究並實作出一個,有效率的追蹤與壓縮方式。 這是一個能針對數位訊號處理器(DSP)的軟硬體研發與驗證有著顯著的幫助的技術。 我們在一個稱為starfish的DSP平台上,將我們的追蹤與偵錯器(Trace Debug Unit)掛上去,並且去追蹤DSP在執行H.264 video decoder與 MP3 decoding時的重要暫存器。 我們提出了幾個方法,針對DSP執行時的program counter(PC)與數十個暫存器特性,來做壓縮,而壓縮的方式是從空間與時間的方向來思考。 經過驗證與實驗後,我們可以將PC壓縮掉87.57%的原始追蹤資料,而壓縮暫存器的部分,則可以達到98.5%的高壓縮率。 此外,我們所提出最好的壓縮方式,可以有forward trace與backward trace的功能。 而這個架構更能夠延伸到即時的追蹤與處理。

In this thesis, we present the efficient debug and trace technology for the embedded DSP core,
which can facilitate the software/hardware co-development and co-verification of the DSP
platform. With the previous constructed DSP platform called Starfish, a test chip and its
prototype are implemented for the demonstration. By evaluating the DSPStone benchmarks
and some realistic multimedia applications such as H.264 and MP3 decodings, we propose
several compression approaches for tracing the content of the program counter and register
file. The compression technique compacts both the spacial and temporal information when
taking advantage of the practical properties of the processor. The compression rate of the
program counter can achieve 87.57% on average; while the compression rate of the register
file is 98.5% as compared with the original raw data.

In addition, the debug and trace design is also implemented, which improves the trace
efficiency as compared with the previous work. The forward and backward trace capability
is also considered in our architecture, making the design practical for both the pre-silicon
validation and post-silicon verification. The architecture can also be extended to process the
real-time tracing if the pipeline scheme is affordable.

Our future works include the further improvement of the compression rate of the traced
data; the support of monitoring the data transactions of the cache and on-chip bus; and the
debug and trace of the multi-core system.

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