對系統設計者而言，減少電力消耗是一項艱鋸的工作。一般可攜帶式系統（如筆記型電腦、手持式裝置）都是消耗電池的電力，因此減少電力消秏即意味著延長電池壽命。在這篇論文中，我提出兩套減少耗能的軟體技術：編譯器技術和作業系統技術。
在編譯器技術方面，我提出一套考量管路硬體架構的資料流分析方法，此方法用來估計某硬體元件在程式中某執行點的活動狀態，以減少未使用元件的漏電消秏。由於切斷某元件電源的時間長短與程式中的分支有關，因此我提出三種針對電源切斷指令的排程機制：Basic_Blk_Sched、MIN_Path_Sched及AVG_Path_Sched。另外，我也將此方法結合到SUIF及MachSUIF編譯器系統中以證實此方法的有效性，我的實驗平台為以具有電源切斷機制的Alpha 21264處理器為平台的模擬器Wattch，實驗結果顯示我們的方法相對於時脈切斷機制，對浮點運算元件可減少82%的電源消耗，而對整體元件而言亦可減少9.9%的電源消秏。

在作業系統方面，我將重點放在即時系統下可變動電壓之處理器的排程問題。我提出一套以知名的EDF (Earliest Deadline First)為基礎的保留表排程演算法以及六套用來決定處理器電壓的演算法。我的實驗是以一套工作集CNC(Computerized Numberical Control)為應用的模擬平台，實驗結果顯示我的可動電壓排程方法相較一般固定電壓排程方法可減少62%的電源消秏。

Reducing power consumption is a crucial challenge to system designers. Portable systems, such as laptop computers and handheld devices, draw power from batteries, so reducing power consumption prolongs battery life. In this thesis, we promote two software techniques for power reduction: the compiler and the operation system solutions.
In the compiler approach, a data-flow analysis framework which estimates the component activities at fixed points of programs with the consideration of pipelines of architectures is proposed to reduce leakage power consumption of useless components. As the duration of power gating on components on given program routines is related to program branches, three scheduling mechanisms for power-gating instructions, called Basic_Blk_Sched, MIN_Path_Sched, and AVG_Path_Sched, are presented and discussed. In addition, we describe a prototype implementation of our approach in SUIF and MachSUIF, a compiler system, to validate the effectiveness. We build the experimental architecture, which is compatible with the DEC Alpha 21264 processor and employs power gating mechanism, within the Wattch simulation environment. The experiments show that our approach reduces average 82% of power consumption for floating-point units and average 9.9% for total power consumption against the clock gating mechanism.

In the operating system approach, we focus the issue on scheduling problems for variable voltage processors in real-time systems. A reservation list scheduling algorithm based on the well-known EDF (Earliest Deadline First) and six decision algorithms which help to decide the voltage of processors are proposed. Also, simulation results of our scheduling polices on a CNC (Computerized Numberical Control) machine controller, a task set, are presented. The simulation results show that our variable voltage scheduling policies is about 62% power reduction against the fixed voltage systems.

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