Multi-phase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this paper we propose a MPCG design with two major contributions: (1) We use a process calibration scheme that makes the per-phase delay (defined as the timing difference between two consecutive clock signals) highly accurate. (2) We further exploit a so-called cyclic property to make the achievable per-phase delay much smaller than a buffer delay. The entire design can be made in nearly standard cells, thus lending itself to automation easily. Using TSMC 0.18um CMOS technology, the experimental results indicate this design is highly general that it can apply to a 16-phase clock signal (with the per-phase delay of only 100ps) for the practical radar SoC design. And it also shows that the phase error can be as high as 188ps without the process calibration, while reduced to less than 13ps after applying the proposed calibration scheme. The proposed MPCG has the RMS and the peak-to-peak jitter of 2.55ps and 22ps at 625MHz, respectively. Besides, it has the area and the power consumption of 0.161mm2 and 49.2mW, respectively.

多相位時脈訊號產生器(Multi-phase Clock Generator, MPCG)主要是用來產生一組時脈訊號它們彼此間具有相同頻率且均勻的相位差。在本篇論文裡，我們提出了一個有兩大特點的多相位時脈訊號產生器(MPCG)：(1) 我們利用製程的校準機制(Process Calibration Mechanism)來使得每一個相位延遲(被定義為兩個連續時脈之間的時間差)更加的精準。(2) 我們提出了利用週期特性來達到讓每一個相位延遲可以小於一個緩衝器(buffer)的延遲。除此之外，在整個多相位時脈訊號產生器(MPCG)電路的設計過程中，可以利用一般標準單元電路(standard cell)的設計流程來實現，這樣不僅可以縮短其電路在更換製程時所耗費的時間，也可以讓電路更容易自動化的來產生。經過佈局後之模擬結果所顯示，在利用TSMC 0.18um之標準單元庫所實現的多相位時脈訊號產生器(MPCG)電路設計，它可以適用於產生16個相位時脈訊號，當輸入頻率為625MHz (週期為1600ps) 時，也就是說每一個相位延遲僅100ps的情況下，利用所提出的製程校準機制可將其最大相位誤差由原本的188ps降至13ps，而所對應的方均根時脈抖動量及峰對峰的時脈抖動量分別為2.55ps與22ps，另外面積跟功率的消耗則分別是0.161mm2與49.2mW。而此16個相位時脈訊號將可以被用於實際雷達系統晶片的設計裡。

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