近年來由於多媒體的普及，使資料傳輸量的需求增加，為了滿足更高速的傳輸速度及更低的成本，高速串列連結(High-Speed-Serial-Link)技術已經廣泛的被應用。此外，隨著電子裝置的操作頻率提高，電磁干擾(EMI)及串音(crosstalk)的問題越顯嚴重，並列輸出會使電路板上繞線更加複雜，因此串列器/解串列器(Serdes)應用在需多高速的傳輸介面，來抵抗這些非理想效應。
本論文在TSMC 65nm CMOS製程下提出了一個應用於2-Gb/s低電壓差動訊號(LVDS)傳輸器，且具有一級後標記前饋式等化器(one-postcursor tap FFE)之預先增強驅動器。隨著資料傳輸頻寬上升達到每秒兆位元的速度，有限頻寬的通道對於訊號傳遞造成嚴重的失真(distortion)，相對的，傳輸端與接收端的設計也將面臨嚴峻的考驗。此外，高速訊號經過傳輸通道由於集膚效應(skin effect)和介電質損耗(dielectric loss)，資料造成嚴重的符號間干擾(ISI)，為了解決上述問題，本論文除了實現了一個將低速並列訊號傳換成高速串列訊號的移位暫存器式的串列器(shift register type serializer)，亦在輸出端加入的可以消除一級後標記的前饋式等化器，來補償通道損耗，使資料經過通道後仍可獲得張開的眼圖(eye diagram)。
除此之外，高速的資料傳輸同時面臨著雜訊及電磁干擾的問題，本論文利用低電壓差動訊號(LVDS)驅動器，藉由其抗共模雜訊及雙端輸出電磁干擾較小的特性，提升資料傳輸的品質。經由模擬驗證，分別通過10到60公分FR4印刷電路板（PCB）通道，最佳可以補償6dB通道耗損。

In recent years, due to the spread of multimedia, the demand for data transmission has increased. In order to meet higher transmission speeds and lower costs, High-Speed-Serial-Link technology has been widely used. In addition, as the operating frequency of the electronic device increases, the problems of electromagnetic interference (EMI) and crosstalk become more serious, and the parallel output makes the winding on the circuit board more complicated, so the serializer/deserializer ( Serdes) is used in many high-speed transmission interfaces to counter these non-ideal effects.
In this thesis, a 2-Gb/s low voltage differential signaling (LVDS) transmitter is proposed in the TSMC 65nm CMOS process with pre-emphasis circuit of one-postcursor tap FFE. As the data transmission bandwidth increases to a speed of megabits per second, the channel with limited bandwidth causes severe distortion to the signal transmission. In contrast, the design of the transmitter and the receiver will also face severe challenges. In addition, high-speed signals pass through the transmission channel due to skin effect and dielectric loss, and the data causes severe inter-symbol interference (ISI). In order to solve the above problem, this thesis implements a shift register type serializer. Low-speed parallel signal is transmitted to the high-speed serial signal. The feedforward equalizer that eliminates one post cursor is added to the output to compensate for the channel loss. An eye-diagram is re-open after passing the data through the channel.
In addition, high-speed data transmission faces both noise and electromagnetic interference problems. This thesis uses low-voltage-differential signaling (LVDS) driver, which owns excellent common-mode noise immunity and can cancel electromagnetic interference by differential schematic. All above these features to improve the quality of data transmission. Through simulation verification, the 10 to 60cm FR4 printed circuit board (PCB) channel is optimally compensated for 6dB channel loss.

[1] T. Instruments, LVDS Owner’s Manual, 2008.
[2] IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), 1596.3 SCI-LVDS Standard, IEEE Std. 1596.3-1996, 1994.
[3] Electrical characteristics of low-voltage differential-signalling (LVDS) interface circuits, TIA/EIA-644, National Semiconductor Corp., ANSI/TIA/EIA, 1996.
[4] B. Reyes, L. Tealdi, G. Paulina, E. Labat, R. Sanchez, P. S. Mandolesi, and M. Hueda, “A 6-bit 2GS/s CMOS Time-Interleaved ADC for Analysis of Mixed-Signal Calibration Techniques,” in IEEE 5th Latin American Symposium on Circuits and Systems, 2014.
[5] A. Boni, A. Pierazzi, and D. Vecchi, “LVDS I/O interface for Gb/sper-pin operation in 0.35- mu;m CMOS,” IEEE Journal of Solid-State Circuits, vol. 36, no. 4, pp. 706 –711, Apr. 2001.
[6]B. Razavi, Design of Analog CMOS Integrated Circuits. 2001.
[7]B. Razavi Design of Integrated Circuits for Optical Communications.
[8] B. Reyes, G. Paulina, L. Tealdi, E. Labat, R. Sanchez, P. S. Mandolesi, and M. Hueda, “A 1.6Gb/s CMOS LVDS Transmitter with a Programmable Pre-Emphasis system ,” in IEEE 5th Latin American Symposium on Circuits and Systems, 2014.