相較於傳統的積體電路，三維積體電路提供了許多益處。現今對三維積體電路主要的研究方向多專注於封裝技術及效能取向，較少考量成本。在本篇論文中，我們提出了一個將製造成本及設計複雜度同時列入考慮的平台式三維積體電路設計方法，將其命名為Chipsburger。並且將此方法實作於一個H.264/AVC影像解碼器。根據我們的實驗結果，我們主張這個平台式三維積體電路設計方法不但可減少設計複雜度、增進能源效率、提高效能，更重要的是此設計方法可有效的降低了一次性工程費用及製造成本。

We propose a platform-based three-dimensional integrated circuit (3D IC) design methodology called Chipsburger. 3D ICs promise many advantages over traditional system-on-a-chip (SoC). Most 3D IC studies address design challenges such as thermal, performance, and floorplanning. Less attention has been paid to cost-driven design. Chipsburger design methodology takes into account both manufacturing cost and design effort. To evaluate our proposed methodology, we implement a H.264/AVC video decoder in Chipsburger 3D IC. Experiments confirm that Chipsburger can reduce non-recurring engineering (NRE) and manufacturing cost, enhance performance, improve energy efficiency, and reduce complexity.

[1]Andrew Chang, "Case Study of a 65-nm SoC Design," IEEE Design and Test Computer, vol. 26, no.2, pp. 14-19, March-April 2009.
[2]Ankur Jain, Robert E Jones, Ritwik Chatterjee, Scott Pozder, and Zhihong Huang, “Thermal Modeling and Design of 3D Integrated Circuits,” Proceedings of Thermal and Thermomechanical Phenomena in Electronic Systems, pp. 1139-1145, May 2008.
[3]A. W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, ”Three-Dimensional Integrated Circuits,” IBM Journal of Research and Development, vol. 50,no. 4, pp. 491-506, July 2006.
[4]Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, and Peter Suaris, “Unified Quadratic Programming Approach for Mixed Mode Placement,” Proceedings of the International Symposium on Physical Design, pp. 193-199, April 2005.
[5]Chia Ming Hung, A Cost Model for Chipsburger – a Platform-Based 3D IC Design, National Tsing Hua University, Hsinchu, Taiwan, pp. 22-27, 2009
[6]C. S. Premachandran, John Lau, Ling Xie, Ahmad Khairyanto, Kelvin Chen, Myo Ei Pa Pa, Michelle Chew, and Won Kyoung Choi “A Novel, Wafer-Level Stacking Method for Low-Chip Yield and Non-Uniform, Chip-Size Wafers for MEMS and 3D SIP Applications,” Proceedings in Electronic Components and Technology Conference, pp. 314-318, May 2008.
[7]Global Unitchip Crop., Available: http://www.globalunichip.com/index.php
[8]Hui Ting Yang, “NTHU H.264/AVC Decoder System,” An Efficient Dictionary-Based Display Frame Compressor, National Tsing Hua University, Hsinchu, Taiwan, pp. 2-6, 2008
[9]International Technology Roadmap for Semiconductors, 1999 Update ITRS. Available: http://www.itrs.net/reports.html
[10]International Technology Roadmap for Semiconductors, 2008 Update ITRS. Available: http://www.itrs.net/reports.html
[11]Jason Cong, Jie Wei, and Yan Zhang, “A Thermal-Driven Floorplanning Algorithm,” Proceedings in International Conference on Computer Aided Design, pp. 306-313, November 2004.
[12]J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright,”Three-Dimensional Silicon Integration,” IBM Journal of Research and Development, vol. 52, no. 6, pp.553-569, November 2008.
[13]LEF/DEF Exchange Format, Si OpenEDA. Available: https://www.si2.org/openeda.si2.org/projects/lefdef
[14]Lei Cheng, Liang Deng, and Martin D.F. Wong, “Floorplan for 3-D VLSI Design,” Proceedings in ASP-DAC Asia and South Pacific, vol. 1, pp. 405-411, January 2005.
[15]Michael Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, and Gabriel H. Loh , “Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 1, January 2007
[16]Prime Time, Synopsys Inc., Available: http://www.synopsys.com/tools/implementation/signoff/pages/primetime.aspx
[17]SoC Encounter RTL-to-GDSII System , Cadence Inc., Available: http://www.cadence.com/products/di/soc_encounter/Pages/default.aspx
[18]UMVP 2500 SoC Platform Document, Global Unichip Corp., Available : http://www.globalunichip.com/4-10.php
[19]W. Rhett Davis, John Wilson, Stephen Mick, Jian Xu, Hao Hua, Christopher Mineo, Ambarish M. Sule, Michael Steer, and Paul D. Franzon, “Demystifying 3D ICs: the pros and cons of going vertical,” IEEE Design and Test Computer, vol. 22, no. 6, pp. 498-510, November-December 2006.
[20]W.-L. Hung, G. M. Link, Yuan Xie, N. Vijaykrishnan, and M. J. Irwin, "Interconnect and Thermal-aware Floorplanning for 3D Microprocessors," Proceedings of International Symposium Quality Electronic Design, pp. 98-104, March 2006.
[21]Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, and Jason Cong1, “Fine Grain 3D Integration for Microarchitecture Design through Cube Packing Exploration,” Proceedings in International Conference on Computer Design, pp. 259-266, October 2004.
[22]0.13 μm Technology, Taiwan Semiconductor Manufacturing Company, Available: http://www.tsmc.com/english/b_technology/b01_platform/b010102_013um.htm