鍺通道之鐵電環繞式閘極場效電晶體與互補式場效電晶體之研究

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研究生：	林宜玟 Lin, Yi-Wen
論文名稱：	鍺通道之鐵電環繞式閘極場效電晶體與互補式場效電晶體之研究 Study of Ge Channel Ferroelectric Gate-all-around Field-effect Transistor and Complementary Field-effect Transistor
指導教授：	吳永俊 Wu, Yung-Chun 侯福居 Hou, Fu-Ju
口試委員:	胡心卉羅廣禮巫勇賢陳健群
學位類別：	博士 Doctor
系所名稱：	原子科學院 - 工程與系統科學系 Department of Engineering and System Science
論文出版年：	2024
畢業學年度：	113
語文別：	英文
論文頁數：	147
中文關鍵詞：	高遷移率通道材料、自發性摻雜、鐵電負電容、奈米線、奈米薄片、環繞式閘極場效電晶體、超晶格、互補式場效電晶體
外文關鍵詞：	high-mobility channel material, self-induced, ferroelectric negative capacitance, nanowire, nanosheet, gate-all-around field-effect transistor (GAAFET), superlattice (SL), complementary field-effect transistor (CFET)
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現代科技的發展推動了5G、物聯網和人工智慧，對效能、功耗和速度的要求也愈加嚴格。技術節點持續微縮，物理限制和製程技術已成為主要挑戰。邏輯元件結構從鰭式演變為環繞式閘極，但僅靠縮短通道長度或減少氧化層厚度，已不足以提升效能和密度，甚至會導致元件失效。為應對這些挑戰，具負電容效應的氧化鉿基材料，因其改善次臨界斜率和降低功耗的優點而成為熱門研究。此外，具高介電常數的氧化層可增加閘極電容，並降低等效氧化層厚度，高載子遷移率材料則可提升驅動電流。為進一步提升電晶體密度，nFET與pFET垂直堆疊的互補式場效電晶體備受關注，此結構能顯著縮小元件尺寸並延續摩爾定律。本論文主要是遵循摩爾定律的發展，探討具高遷移率通道之鐵電負電容場效電晶體與互補式場效電晶體。本論文共可分成三個部分，(1)自發性鍺摻雜氧化鉿之鍺奈米線鐵電負電容環繞式閘極場效電晶體，以及鍺堆疊奈米線環繞式閘極場效電晶體，(2)使用高介電常數氧化層之鍺奈米薄片環繞式閘極場效電晶體，(3)鍺奈米線和矽鰭結構之互補式場效電晶體與方形鍺和菱形鍺奈米線結構之互補式場效電晶體。
第1部份（第二至四章）為鍺奈米線環繞式閘極場效電晶體之研究。利用Ge在高溫下會解吸並摻入HfO2，形成具鐵電負電容性質的Ge摻雜HfO2薄膜(Ge:HfO2)，並探討其在不同退火溫度下的變化。將此薄膜應用在奈米線環繞式閘極結構，其次臨界擺幅(SS)可低於物理極限60 mV/decade，具有高效能、低功耗的特性。接著探討鍺堆疊菱形奈米線環繞式閘極場效電晶體的元件特性，菱形結構具有良好的載子遷移率和較低的介面缺陷能態，堆疊的結構則可以減少寄生電容並增加驅動電流，並使用Sentaurus TCAD針對此結構進行模擬，得到其適用於3奈米以下的技術節點。此外，探討不同介面層形成方式以及HfO2和Al2O3的厚度對Ge:HfO2的影響，並將此薄膜應用在堆疊的奈米線結構，得到SS可低於60 mV/decade的特性。
第2部份（第五章）設計每層厚度不同的超晶格氧化鉿/氧化鋯的薄膜(每層0.3奈米氧化鉿/0.3奈米氧化鋯、每層0.5奈米氧化鉿/0.5奈米氧化鋯、每層1奈米氧化鉿/1奈米氧化鋯)，並使用電容去驗證其介電常數、極化，以及介面能態缺陷。比較這些特性後，使用每層厚度為0.3奈米氧化鉿/0.3奈米氧化鋯，作為鍺堆疊奈米薄片環繞式閘極場效電晶體的氧化層，以增加閘極電容並提升驅動電流。
第3部分（第六至七章）提出並實際製作: 鍺奈米線在矽鰭上之互補式場效電晶體，以及方形鍺奈米線在菱形鍺奈米線上之互補式場效電晶體，皆使用單一金屬作為閘極。這兩種互補式場效電晶體皆相容於目前的技術平台，且可以簡化製程，展現出適用於1奈米技術節點的潛力。

The development of modern technology has driven demand for 5G, the Internet of Things (IoT), and artificial intelligence (AI), resulting in increasingly stringent requirements for performance, power consumption, and speed. As technology nodes continue to scale down, physical limitations and process technology have become major challenges. The structure of logic devices has evolved from FinFETs to gate-all-around (GAA) FETs, but simply shortening the channel length or reducing the oxide thickness is insufficient to improve performance and density and may even result in device failure. To address these challenges, hafnium oxide-based materials with negative capacitance effects have become a popular research focus due to their advantages in improving the subthreshold slope and reducing power consumption. Additionally, gate oxides with high dielectric constants can increase gate capacitance and reduce the equivalent oxide thickness, while materials with high carrier mobility can enhance the drive current. To further increase transistor density, vertically stacked nFET and pFET complementary field-effect transistors (CFETs) attract attention, as this structure can significantly reduce device size and extend Moore's Law. This dissertation primarily aims to extend Moore's Law by investigating ferroelectric (Fe) negative capacitance field-effect transistors (NCFETs) and CFETs with high-mobility channel materials. The dissertation is divided into three parts: (1) Ge nanowire (NW) ferroelectric negative capacitance GAAFET with self-induced Ge doped HfO2 and Ge stacked diamond-shaped NWs GAAFETs, (2) Ge stacked nanosheets GAAFET with high dielectric constant gate oxide, and (3) Ge NW on Si Fin CFET and Ge rectangle NW on Ge diamond NW CFET.
The first part (Chapters 2 to 4) focuses on the study of Ge NW GAAFET. It investigates Ge desorption and incorporation into HfO2 at high temperatures to form a ferroelectric negative capacitance Ge-doped HfO2 (Ge:HfO2) thin film, and explores this phenomenon at different annealing temperatures. The Ge:HfO2/Al2O3 as the gate stack was then applied to a Ge NW Fe-GAAFET. The device shows a steep subthreshold slope and a high ION/IOFF ratio. Next, the stacked diamond-shaped Ge NWs GAAFET was investigated. The diamond structure provides excellent carrier mobility and lower interface trap density, while the stacked structure minimizes parasitic capacitance and increases the drive current. Sentaurus TCAD simulations demonstrate the potential of this structure for sub-3nm technology node logic applications. Further investigations explore the influence of different interfacial layer formation methods and the thicknesses of HfO2 and Al2O3 on the self-induced ferroelectric Ge:HfO2 thin film. The optimized conditions were applied to the stacked NWs structure and achieved SS below 60 mV/decade.
The second part (Chapter 5) presents the design of HfO2/ZrO2 superlattice (SL) with varying layer thicknesses (0.3-nm HfO2/0.3-nm ZrO2, 0.5-nm HfO2/0.5-nm ZrO2, 1-nm HfO2/1-nm ZrO2). Capacitors were used to evaluate the dielectric constant, polarization, and interface trap density. After comparing these properties, the 0.3-nm HfO2/0.3-nm ZrO2 SL was selected as the gate stack for the Ge stacked nanosheets GAAFET to increase the gate capacitance and enhance the drive current.
The third part (Chapters 6 to 7) proposes and experimentally fabricates the self-aligned stacked Ge NW pGAAFET on Si nFinFET of single-gate CFET and the self-aligned stacked hetero-oriented p-type Ge rectangle NW GAAFET on n-type Ge diamond NW GAAFET of single-gate CFET. Both CFETs are fully compatible with current Si technology platforms and can simplify the fabrication process, demonstrating the potential for scaling toward the N1 node.

中 文 摘 要    i
Abstract    iii
Acknowledgment    vi
Contents    vii
List of Tables    xi
List of Figures    xii
Chapter 1 Introduction    1
1 Challenges of Moore's Law and Opportunities    1
2 High mobility channel materials    4
3 Evolution of Transistor Architecture    7
3.1 Multi-Gate Field-Effect Transistor    10
3.2 Complementary Field-Effect Transistor    12
4 Logic Applications of Hafnium Oxide Based Materials    14
4.1 Ferroelectric Negative Capacitance (NC) Field-Effect Transistor    15
4.2 Higher Dielectric constant of Superlattice (SL) HfO2/ZrO2    21
5 Organization of the Dissertation    26
6 References    28
Chapter 2 Self-induced ferroelectric 2-nm-thick Ge-doped HfO2 thin film applied to Ge nanowire ferroelectric gate-all-around field-effect transistor    36
1 Motivation and Literature Review    36
2 Experimental    38
3 Results and Discussion    40
4 Summary    47
5 References    48
Chapter 3 Tightly Stacked 3D Diamond-Shaped Ge Nanowire Gate-All-Around FETs With Superior nFET and pFET Performance    53
1 Motivation and Literature Review    53
2 Experimental    55
3 Results and Discussion    57
4 Summary    64
5 References    65
Chapter 4 Self-Induced Ge-Doped HfO2 Applied to Ge Stacked Nanowires Ferroelectric Gate-All-Around Field-Effect Transistor with Steep Subthreshold Slope Under O3 Treatment with GeO2 as Interfacial Layer    70
1 Motivation and Literature Review    70
2 Experimental    72
3 Results and Discussion    75
3.1 Characteristic of self-induced Ge:HfO2 MFIS capacitors with three IL treatments    75
3.2 Ferroelectric effect applies on Ge stacked NWs GAAFET    78
4 Summary    80
5 References    81
Chapter 5 Using High Dielectric Constant HfO2/ZrO2 Superlattice Dielectrics to Enhance Ge Stacked Nanosheets Gate-All-Around Transistor Performance    87
1 Motivation and Literature Review    87
2 Experimental    88
3 Results and Discussion    91
4 Summary    96
5 References    97
Chapter 6 3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET    102
1 Motivation and Literature Review    102
2 Experimental    103
3 Results and Discussion    107
4 Simulation    112
5 Summary    115
6 References    116
Chapter 7 3-D Self-Aligned Stacked Ge Nanowires Complementary FET Featuring Single Gate Simple Process    122
1 Motivation and Literature Review    122
2 Experimental    124
3 Results and Discussion    127
4 Summary    132
5 References    133
Chapter 8 Conclusion    140
Curriculum Vitae    142
Publication List    143
Appendix    146


                                

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