本論文主題在於使用標準互補式金氧半製程，研究和實現具有單晶低成本的射頻前端積體電路之方法。第一章為簡介，而論文內容可分為兩部份：第二章和第三章為第一部份，主要分別為元件層級；第四章和第五章為第二個部份，主要為電路和系統層級。最後，第六章為結論和未來展望。
第二章介紹並推導了單晶電感的理論和各項參數，並提出改善多層並聯結構的電感，不但改善了品質因素(15%)，也大幅改善了自我共振頻率(25%)，更進一步具有可配置及適應性的能力，使其適用於任何的規格，因此可以達到最佳化，進而擁有高競爭力。另外，將其推廣至對稱的型式，使其適用於差動電路，並提出改善更多的多層並聯結構之對稱電感，在幾乎相同感值下大大的改善了自我共振頻率(50%)，使得其適應性和最佳化範圍更廣，藉由較高的電感除以電容比，可降低電路的功率消耗和改善電路的特性，相較於傳統兩個非對稱電感，其節省了百分之二十五的面積佔據。在大感值的應用方面，微型3-D電感是不錯的選擇，但在差動電路中，我們提出了微型3-D對稱電感的結構和想法。

第三章介紹並闡述了單晶變壓器的理論和各項參數，經由第二章的改善多層並聯結構之觀念，我們可以將此應用於傳統平面變壓器中，進而在主和副線圈幾乎相同感值下來調整其通過和拒斥頻段，因此具有可配置的能力。為了進一步降低成本，我們提出微型3-D變壓器，由於其為對稱的型式，使其十分適合取代差動電路中的兩個非對稱電感；相較於傳統平面變壓器，其節省了大約百分之七十的面積；相較於傳統疊接變壓器，其具有較寬的可用頻寬和較高的自我共振頻率。

第四章介紹雙頻接收器的演進，以及我們所採用的同時雙頻接收器架構，接著則是呈現所製作的同時雙頻低雜訊放大器，以及為了改善雜訊指數和鏡頻拒斥比的新穎型帶拒濾波器，相較於傳統電感、電容並聯共振網路其2.4-GHz和5.3-GHz的介入損耗達到最小，而且其鏡頻(3.4-GHz)拒斥深度改善超過12dB，使其非常適合使用於同時雙頻接收機中，作為射頻鏡頻拒斥，用來克服降頻和低頻部份的增益和相位不平衡誤差所導致的鏡頻拒斥比退化。

第五章介紹電感電容壓控振盪器，藉由同時切換電感和變電容器，可達到雙中心振盪頻率，故所製作的雙頻壓控振盪器將可克服隨著製程精進，操作電壓持續降低，造成變電容器可調整的範圍減小之問題。

第六章總結了之前各章節的結果，並加強說明低成本、高競爭力的目的和成效，以及未來的展望。

The purpose of this work is to use a standard CMOS process to research and implement the solutions of monolithic and low cost RF front-end integrated circuits. The first chapter is an introduction, and the content of this thesis is divided into two parts. The first part is chapter 2 and 3, in which the device level is presented. Chapter 4 and 5 is the second part and the circuit and system level is presented. Finally, chapter 6 is the conclusion and future work.
The theory and parameters of monolithic inductor are introduced and derived in chapter 2 and the structure of our proposed improved multilevel-shunting (IMS) spiral inductor is presented. It not only improves the quality factor, Q (15%) but also improves the self-resonant frequency, fSR (25%) greatly. Moreover, the configurable and adaptive ability to make it applicable to any specification, therefore the optimization can be done and the high competition is achieved. Besides, we expand it to symmetric configurations for the differential circuit applications, and the structure of our proposed further improved multilevel-shunting (FIMS) symmetric spiral inductor is presented. There is up to 46% improvement in fSR and without deteriorating the Q compared to the conventional multilevel-shunting (MS) spiral inductor with almost the same inductance, thus the configurable and optimal range is extended. By virtue of leading to a higher L/C ratio, the power consumption and characteristic of the circuit can be improved. Furthermore, it saves 25% area occupied compared to two asymmetric inductors. For the large inductance applications, the miniature 3-D inductor is a good choice. For the differential circuits, the structure and idea of miniature 3-D symmetric inductor are presented.

The theory and parameters of monolithic transformer are introduced and derived in chapter 3. By way of the idea of IMS structure in chapter 2, we can use it in conventional interleaved transformers to adjust their pass and reject band with almost the same inductance of primary and secondary coils, therefore also having the configurable ability. In order to further reduce the cost, we present the miniature 3-D transformer. Due to its symmetric configuration, it is very suitable to replace two asymmetric inductors in differential circuit. Moreover, it saves about 70% area compared to the conventional planar transformer, and has wider available bandwidth and higher self-resonant frequency compared to the conventional stacked transformer.

The evolution of dual-band receiver and the concurrent dual-band receiver we used are introduced in chapter 4. The concurrent dual-band low noise amplifier and novel notch filter for improving noise figure and image-reject ratio are implemented and measured. It achieves the less insertion loss in 2.4-GHz and 5.3-GHz band compared to conventional LC parallel resonant network and the depth of image (3.4-GHz) rejection improves over 12dB. Therefore, it is very suitable in concurrent dual-band receiver for RF image-rejection to overcome the image-reject ratio degrading due to gain and phase imbalances in down-conversion and baseband parts.

The LC tank voltage-controlled oscillator is presented in chapter 5. By switching the inductor and varactor simultaneously, the dual center frequencies are achieved. Therefore, the dual-band VCO can overcome the problem resulted from the tuning range of varactor is limited as the process progress and supply voltage scaled down.

The results are summarized in chapter 6 and we expound the goal and effect of low cost and high competition, and the future work.

[1] D. K. Shaffer, and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745-759, May 1997.
[2] J. Craninckx, and M. S. J. Steyaert, “A 1.8-GHz Low-Phase Noise CMOS VCO Using Optimized Hollow Spiral Inductors,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 736-744, May 1997.
[3] M. Niknejad, and R. G. Meyer, Design, Simulation and Applications of Inductors and Transformers for Si RF ICs, Kluwer Academic 2000.
[4] J. R. Long, and M. A. Copeland, “The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC’s,” IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 357-369, Mar. 1997.
[5] C. P. Yue, and S. S. Wong, “Physical Modeling of Spiral Inductors on Silicon,” IEEE Trans. Electron Devices, vol. 47, no. 3, pp. 560-568, Mar. 2000.
[6] A. Zolfaghari, A. Chan, and B. Razavi, “Stacked Inductors and Transformers in CMOS Technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628, Mar. 2001.
[7] S. S. Mohan, M. d. M. Hershenson, S. P. Boyd, and T. H. Lee, “Simple Accurate Expressions for Planar Spiral Inductances,” IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1419-1424, Oct. 1999.
[8] M. Park, S. Lee, C. S. Kim, H. K. Yu, and K. S. Nam, “The Detailed Analysis of High Q CMOS-Compatible Microwave Spiral Inductors in Silicon Technology,” IEEE Trans. Electron Devices, vol. 45, no. 9, pp. 1953-1959, Sep. 1998.
[9] C. P. Yue, and S. S. Wong, “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC’s,” IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 743-752, May 1998.
[10] J. M. Lopez-Villegas, J. Samitier, C. Cane, P. Losantos, and J. Bausells, “Improvement of the Quality Factor of RF Integrated Inductors by Layout Optimization,” IEEE Trans. Microwave Theory Tech., vol. 48, no. 1, pp. 76-83, Jan. 2000.
[11] J. N. Burghartz, M. Soyuer, and K. A. Jenkins, “Microwave inductors and capacitors in standard multilevel interconnect silicon technology,” IEEE Trans. Microwave Theory Tech., vol. 44, no. 1, pp. 100-104, Jan. 1996.
[12] S.-M. Yim, and Kenneth K.O., “Demonstration of a Switched Resonator Concept in a Dual-Band Monolithic CMOS LC-Tuned VCO,” IEEE Custom Integrated Circuits Conference, pp. 205-208, 2001
[13] H. Hashemi, A. Hajimiri, “Concurrent Multiband Low-Noise Amplifiers – Theory, Design, and Applications,” IEEE Trans. Microwave Theory Tech., vol. 50, no. 1, pp. 100-104, Jan. 2002.
[14] W. B. Kuhn, and N. M. Ibrahim, “Analysis of Current Crowding Effects in Multiturn Spiral Inductors,” IEEE Trans. Microwave Theory Tech., vol. 49, no. 1, pp. 31-38, Jan. 2001.
[15] M. W. Green, G. J. Green, R. G. Arnold, J. A. Jenkins, and R. H. Jansen, “Miniature multiplayer spiral inductors for GaAs MMICs,” in GaAs IC Symp., pp. 303-306, 1989.
[16] C.-C. Tang, C.-H. Wu, and S.-I. Liu, “Miniature 3-D Inductors in Standard CMOS Process,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 471-480, Apr. 2002.
[17] W. B. Kuhn, A. Elshabini-Riad, and F. W. Stephenson, “Centre-tapped spiral inductors for monolithic bandpass filters,” IEEE Electronics Letters, vol. 31, no. 8, pp. 625-626, Apr. 1995.
[18] M. Tiebout, “Low-Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1018-1024, July 2001.
[19] M. Danesh, and J. R. Long, “Differentially Driven Symmetric Microstrip Inductors,” IEEE Trans. Microwave Theory Tech., vol. 50, no. 1, pp. 332-341, Jan. 2002.
[20] H. B. Erzgraber, M. Pierschel, G. G. Fischer, Th. Grabolla, and A. Wolff, “High Performance Integrated Spiral Inductors Based on a Minimum AC Difference Voltage Principle,” IEEE Topical Meeting on Digest of Silicon Monolithic Integrated Circuits in RF Systems, pp. 71-74, 2000.
[21] T. H. Lee and A. Halimiri, The Design of Low Noise Oscillators, Kluwer Academic Publishers, Norwell, MA, 1999.
[22] C. Liao, T. Huang, C. Lee, D. Tang, S. Lan, T. Yang, and L. Lin, “Method of creating local semi-insulating regions on silicon wafers for device isolation and realization of high-Q inductor,” IEEE Electron Device Letters, pp. 461-462, Dec. 1998.
[23] L. Lu, G. E. Ponchak, P. Bhattacharya, and L. P. B. Katehi, “High-Q X-band and K-band micromachined spiral inductors for use in Si-based integrated circuits in RF systems,” IEEE Topical Meeting on Digest of Silicon Monolithic Integrated Circuits in RF Systems, pp. 108-112, 2000.
[24] M. Ozgur, M. E. Zaghloul, and M. Gaitan, “High Q backside micromachined CMOS inductors,” Proceedings of the IEEE Int. Symp. on Circuits and Systems, vol. 2, pp. 577-580, 1999.
[25] J. N. Burghartz, “Progress in RF Inductors on Silicon – Understanding Substrate Losses,” in Int. Electron Devices Meet. Tech. Dig., pp. 523-526, 1998.
[26] P. H. Young, Electronic Communication Techniques fourth edition, Prentice Hall International 1999.
[27] Y. E. Chen, D. Bien, D. Heo, and J. Laskar, “Q-Enhancement of Spiral Inductors with N+-Diffusion Patterned Ground Shields,” IEEE MTT-S Int. Digest of Microwave Symp., vol. 2, pp.1289-1292, 2001.
[28] J. N. Burghartz, A. E. Ruehli, K. A. Jenkins, M. Soyuer, and D. Nguyen-Ngoc, “Novel Substrate Contact Structure for High-Q Silicon-Integrated Spiral Inductors” in Int. Electron Devices Meet. Tech. Dig., pp. 55-58, 1997.
[29] A. L. L. Pun, T. Yeung, J. Lau, F. J. R. Clement, and D. K. Su, “Substrate Noise Coupling Through Planar Spiral Inductor,” IEEE J. Solid-State Circuits, vol. 33, no. 6, pp. 877-884, June 1998.
[30] T. Yeung, A. Pun, Z. Chen, J. Lau, F. J. R. Clement, “Noise Coupling in Heavily and Lightly Doped Substrate from Planar Spiral Inductor,” Proceedings of IEEE Int. Symp. on Circuits and Systems, vol. 2, pp. 1405-1408, 1997.
[31] K. Kim, and K. O, “Characteristics of an Integrated Spiral Inductor with an Underlying n-Well” IEEE Trans. on Electron Devices, vol. 44, no. 9, pp. 1565-1567, Sep. 1997.
[32] F. Mernyei, F. Darrer, M. Pardoen, and A. Sibrai, “Reducing the Substrate Losses of RF Integrated Inductors,” IEEE Microwave and Guided Wave Letters, vol. 8, no. 9, Sep. 1998.
[33] Q. Chen, B. Agrawal, and J. D. Meindl, “A Novel Geometry for Circular Series Connected Multilevel Inductors for CMOS RF Integrated Circuits,” IEEE Trans. on Electron Devices, vol. 49, no. 6, pp. 1084-1086, Jane 2002.
[34] K. T. Ng, B. Rejaei, and J. N. Burghartz, “Substrate Effects in Monolithic RF Transformers on Silicon” IEEE Trans. Microwave Theory Tech., vol. 50, no. 1, pp. 377-383, Jan. 2002.
[35] J. R. Long, “Monolithic Transformers for Silicon RF IC Design” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1368-1382, Sep. 2000.
[36] C.-C. Tang, and S.-I. Liu, “Low-voltage CMOS low-noise amplifier using planar-interleaved transformer,” IEEE Electronics Letters, vol. 37, no. 8, Apr. 2001.
[37] J. J. Zhou, and D. J. Allstot, “Monolithic Transformers and Their Application in a Differential CMOS RF Low-Noise Amplifier,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2020-2027, Dec. 1998.
[38] S. Wu, and B. Razavi, “A 900-MHz/1.8-GHz CMOS Receiver for Dual-Band Applications” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2178-2185, Dec. 1998.
[39] A. A. Abidi, “Direct-Conversion Radio Transceivers for Digital Communications,” IEEE J. Solid-State Circuits, vol. 30, no. 12, pp. 1399-1410, Dec. 1995.
[40] J. R. Long, and M. C. Maliepaard, “A 1V 900MHz Image-Reject Downconverter in 0.5μm CMOS,” IEEE Custom Integrated Circuits Conference, pp. 665-668, 1999.
[41] J. C. Rudell et al., “A 1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2071-2087, Dec. 1997.
[42] J. Crols, and M. Steyaert, “A Single-Chip 900MHz CMOS Receiver Front-End with a High Performance Low-IF Topology,” IEEE J. Solid-State Circuits, vol. 30, no. 12, pp. 1483-1492, Dec. 1995.
[43] S. Lee et al., “A 1GHz Image-Rejection Down-Converter in 0.8μm CMOS Technology,” IEEE Transactions on Consumer Electronics, vol. 44, no. 2, pp. 235-239, 1998.
[44] B. Razavi, RF Microelectronics, NJ: Prentice Hall, Upper Saddle River, 1998.
[45] J. P. Maligeorgos, and J. R. Long, “A Low-Voltage 5.1-5.8-GHz Image-Reject Receiver with Wide Dynamic Range,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1917-1926, Dec. 2000.
[46] T. Okanobu, D. Yamazaki, and C. Nishi, “A New Radio Receiver System for Personal Communications,” IEEE Transactions on Consumer Electronics, vol. 41, no. 3, pp. 795-803, Aug. 1995.
[47] M. Banu et al., “A BiCMOS Double-Low-IF Receiver for GSM,” IEEE Custom Integrated Circuits Conference, pp. 521-524, 1997.
[48] F. Behbahani, et al., “A 2.4-GHz Low-IF Receiver for Wideband WLAN in 0.6-μm CMOS - Architecture and Front-End,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1908-1916, Dec. 2000.
[49] Y. J. Kim, H. C. Park, I. K. Nam, and K. Lee, “Architecture and algorithm for ultra-high precision image rejection mixer using digital compensation,” IEE Electronics Letters, vol. 36, no. 19, pp. 1604-1606, Sep. 2000.
[50] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, chapter 11, 1998.
[51] A. N. L. Chan, C.B. Guo, and H. C. Luong, “A 1-V 2.4-GHz LNA with Source Degeneration as Image-Rejection Notch Filter,” IEEE International Symposium on Circuits and Systems, vol. 4, pp. 890-893, 2001.
[52] D. R. Pehlke, A. Burstein, and M. F. Chang, “Extremely high-Q tunable inductor for Si-based RF integrated circuit applications,” in Int. Electron Devices Meet. Tech. Dig., pp. 63-66, 1997.
[53] B. Ray, J. S. Hamel, T. Manku, and J. J. Nisbet, “A highly selective passive band reject filter with Low-Q lumped elements in a Si bipolar,” Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, pp. 168-171, 2000.
[54] H. Samavati, H. R. Rategh, and T. H. Lee, “A 5-GHz CMOS Wireless LAN Receiver Front End,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 765-772, May 2000.
[55] A. Van der Ziel, Noise in solid state devices and circuits, New York: Wiley, 1986.
[56] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
[57] T. Soorapanth, and S. S. Wong, “A 0-dB IL 2140 ± 30 MHz Bandpass Filter Utilizing Q-Enhanced Spiral Inductors in Standard CMOS,” IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 579-586, May 2002.
[58] B. A. Floyd, J. Mehta, C. Gamero, and K. K. O, “A 900-MHz, 0.8-μm CMOS Low Noise Amplifier with 1.2-dB Noise Figure,” Proceedings of the IEEE Custom Integrated Circuits, pp. 661-664, 1999.
[59] Hao-Shun Yang, Bachelor Thesis: Design and Realization of 2.4GHz CMOS RF Image-Reject Low Noise Amplifier and High Quality Factor Si-based Spiral Inductors, Nov. 2000.
[60] S. Wolf, Silicon Processing for the VLSI Era, Volume 3: The Submicron MOSFET. Sunset Beach, California: Lattice Press, 1995.
[61] F. M. Klaassen, “High Frequency Noise of the Junction Field-Effect Transistor,” IEEE Trans. on Electron Devices, vol. ED-14, no. 7, pp. 368-373, July 1967.
[62] P. Andreani, and H. Sjoland, “Noise Optimization of an Inductively Degenerated CMOS Low Noise Amplifier,” IEEE Trans. on Circuit and Systems -Ⅱ: Analog and Digital Signal Processing, vol. 48, no. 9, pp. 835-841, Sep. 2001.
[63] H.-Y. Tsui, and J. Lau, “SPICE Simulation and Tradeoffs of CMOS LNA Performance with Source-Degeneration Inductor,” IEEE Trans. on Circuit and Systems -Ⅱ: Analog and Digital Signal Processing, vol. 47, no. 1, pp. 62-65, Jan. 2000.
[64] J. Chen, and B. Shi, “Impact of Intrinsic Channel Resistance on Noise Performance of CMOS LNA,” IEEE Electron Device Letters, vol. 23, no. 1, pp. 34-36, Jan. 2002.
[65] C.-Y. Lin , RF CMOS IC Design Flow, CIC Training Manual, July 2000.
[66] C.-H. Feng, F. Jonsson, M. Ismail, and H. Olsson, “Analysis of nonlinearities in RF CMOS amplifiers,” Proceedings of the 6th IEEE International Conference on Electronics Circuits and Systems, vol. 1, pp.137-140, 1999.
[67] H.-S. Kim, X. Li, and M. Ismail, “A 2.4 GHz CMOS low noise amplifier using an inter-stage matching inductor,” 42nd Midwest Symposium on Circuits and Systems, vol. 2, pp. 1040-1043, 2000.
[68] X. Li, H.-S. Kim, M. Ismail, and H. Olsson, “A novel design approach for GHz CMOS low noise amplifiers,” IEEE Radio and Wireless Conference, pp. 285-288, 1999.
[69] C.-Y. Cha, and S.-G. Lee, “A low power, high gain LNA topology,” 2nd International Conference on Microwave and Millimeter Wave Technology, pp. 420-423, 2000.
[70] C.-C. Hsiao, M.-S. Chen, and Y.-C. Chiang, “A low noise NMOSFET with overlaid metal gate,” IEEE MTT-S International Microwave Symposium Digest, vol. 3, pp. 1711-1714, 1998.
[71] L. MacEachern, and T. Manku, “Metal-over-gate MOSFET modeling for radio frequency IC applications,” Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 2, pp. 164-167, 2000 Geneva.
[72] T. Manku, “Microwave CMOS – Device Physics and Design,” IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 277-285, Mar. 1999.
[73] T. Manku, “Microwave CMOS – Devices and Circuits,” IEEE Custom Integrated Circuits Conference, pp. 59-66, 1998.
[74] G. Gramegna, M. Paparo, P. G. Erratico, and P. D. Vita, “A Sub-1-dB NF ±2.3-kV ESD-Protected 900-MHz CMOS LNA,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1010-1017, July 2001.
[75] R. P. Jindal, “Distributed substrate resistance noise in fine-line NMOS field-effect transistors,” IEEE Trans. on Electron Devices, vol. ED-32, no. 11, pp. 2450-2453, Nov. 1985.
[76] A. Rofougaran, J. Y.-C. Chang, M. Rofougaran, and A. A. Abidi, "A 1 GHz CMOS RF Front-End IC for a Direct-Conversion Wireless Receiver," IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 880-889, July 1996.
[77] C. S. Kim, J.-W. Park, H. K. Yu, and H. Cho, "Gate Layout and Bonding Pad Structure of a RF n-MOSFET for Low Noise Performance," IEEE Electron Device Letters, vol. 21, no. 12, pp. 607-609, Dec. 2000.
[78] T. E. Kolding, "Shield-Based Microwave On-Wafer Device Measurements," IEEE Trans. Microwave Theory Tech., vol. 49, no. 6, pp. 1039-1044, June 2001.
[79] M.-D. Ker, H.-C. Jiang, and C.-Y. Chang, "Design on the Low-Capacitance Bond Pad for High-Frequency I/O Circuits in CMOS Technology," IEEE Trans. on Electron Devices, vol. 48, no. 12, pp. 2953-2956, Dec. 2001.
[80] P. Arcioni, R. Castello, L. Perregrini, E. Sacchi, and F. Svelto, “An improved lumped-element equivalent circuit for on silicon integrated inductors,” IEEE Radio and Wireless Conference, pp. 301-304, 1998.
[81] C. B. Sia et al., “A Simple and Scalable Model for Spiral Inductors on Silicon,” Modeling and Simulation of Microsystems, 2001.
[82] D. Melendy et al., “A New Wide-Band Compact Model for Spiral Inductors in RFICs,” IEEE Electron Device Letters, vol. 23, no. 5, pp. 273-275, May 2002.
[83] L.F. Tiemeijer, D.M.W. Leenaerts, N. Pavlovic, and R.J. Havens, “Record Q Spiral Inductors in Standard CMOS,” in Int. Electron Devices Meet. Tech. Dig., pp. 40.7.1-40.7.3, 2001.
[84] Y. Cao et al., “Frequency-Independent Equivalent Circuit Model for On-chip Spiral Inductors,” Custom Integrated Circuits Conference, pp 217-230, 2002.
[85] C.-H. Wu, C.-C. Tang, and Shen-Iuan Liu, “Analysis of On-Chip Spiral Inductors Using the Distributed Capacitance Model,” IEEE Asia-Pacific Conference on ASICs (AP-ASIC), Aug. 2002.
[86] A. M. Niknejad and R. G. Meyer, Design, Simulation and Applications of inductors and transformers for Si RF ICs, Kluwer Academic Publishers, 2000.
[87] D. Kehrer, W. Simburger, H.-D. Wohlmuth, and A.L. Scholtz, “Modeling of monolithic lumped planar transformers up to 20 GHz,” IEEE Conference on Custom Integrated Circuits, pp. 401-404, 2001.
[88] J. J. Rael, and A. A. Abidi, “Physical Processes of Phase Noise in Differential LC Oscillators,” IEEE Custom Integrated Circuits Conference, pp. 569-572, 2000.
[89] D. Ham, and A. Hajimiri, “Concepts and Methods in Optimization of Integrated LC VCOs,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 896-909, June 2001.
[90] E. Hegazi, H. Sjoland, and A. A. Asad, “A Filtering Technique to Lower LC Oscillator Phase Noise” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001.
[91] C.-M. Hung, B. A. Floyd, N. Park, and K. K. O, “Fully Integrated 5.35-GHz CMOS VCOs and Prescalers,” IEEE Trans. Microwave Theory Tech., vol. 49, no. 1, pp. 17-22, Jan. 2001.
[92] P. Andreani, and H. Sjoland, “Tail Current Noise Suppression in RF CMOS VCOs,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 342-348, Mar. 2002.
[93] A. Hajimiri, and T. H. Lee, “Design Issues in CMOS Differential LC Oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717-724, May 1999.
[94] C.R.C. D. Ranter, and M.S.J. Steyaert, “A 0.25μm CMOS 17GHz VCO,” IEEE International Solid-State Circuits Conference (ISSCC), pp.370-371, 466, 2001.
[95] F. Herzel, H. Erzgraber, and N. Ilkov, “A New Approach to Fully Integrated CMOS LC-Oscillators with a Very Large Tuning Range,” IEEE Custom Integrated Circuits Conference, pp. 573-576, 2000.
[96] F. Herzel, H. Erzgraber, and P. Weger, “Integrated CMOS wideband oscillator for RF applications,” IEE Electronics Letters, vol. 37, no. 6, pp. 330-331, Mar. 2001.
[97] S.-M. Yim, and K. K.O, “Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC-tuned VCO,” IEEE Conference on Custom Integrated Circuits, pp. 205-208, 2001.
[98] L. Dauphinee, M. Copeland, and P. Schvan, “A Balanced 1.5GHz Voltage Controlled Oscillator with an Integrated LC Resonator,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 390-391, 491, 1997.
[99] R. Aparicio, and A. Hajimiri, “A CMOS Differential Noise-Shifting Colpitts VCO,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 288-289, 2002.
[100] A. Hajimiri, and T. H. Lee, The Design of Low Noise Oscillators, Kluwer Academic Publishers, Norwell, MA, 1999.
[101] C.-M. Hung, Y.-C. Ho, I-C. Wu, and K. O, “High-Q Capacitors Implemented in a CMOS Process for Low-Power Wireless Applications,” IEEE Trans. Microwave Theory Tech., vol. 46, no. 5, pp. 505-511, May 1998.
[102] D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, pp. 329-330, Feb. 1966.
[103] J. Craninckx, and M. Steyaert, Wireless CMOS Frequency Synthesizer Design, Kluwer Academic Publishers, Norwell, MA, 1998.
[104] R. Mongia, I. Bahl, and P. Bhartia, RF and Microwave Coupled-Line Circuits, Artech House, 1999.
[105] T. Liang, J. Gillis, D. Wang, and P. Cooper, “Design and Modeling of Compact On-Chip Transformer/Balun Using Multi-Level Metal Windings for RF Integrated Circuits,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 117-120, 2001.