橫向型擴散金氧半場效電晶體之非匹配特性研究

簡易檢索 / 詳目顯示

回結果列表

研究生：	廖唯理 Wei-Li Liao
論文名稱：	橫向型擴散金氧半場效電晶體之非匹配特性研究 Study of the LDMOSFET Mismatch Characteristics
指導教授：	龔正 Jeng Gong
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	中文
論文頁數：	136
中文關鍵詞：	非匹配、橫向型擴散金氧半場效電晶體、高功率元件、精準度
外文關鍵詞：	Mismatch, LDMOSFET, Power devices, Precision
相關次數：	點閱：2 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

隨著半導體產業的發展，高功率元件經常被應用於許多電力電子方面。功率元件為了與平面製程整合，需將傳統垂直式之元件結構改成橫向式的設計，因而可與低壓電路整合於同一晶片上。藉由元件模擬軟體TCAD 的使用，我們能更瞭解元件內部操作原理。最後將透過軟體電腦模擬的方式，可以清楚知道在不同條件設定下的非匹配特性，有效的掌握元件於最佳化之結果。

非匹配對元件之衝擊越來越重要主要是因為元件線寬越來越小，針對元件中啟始電壓、飽和電流與電導的非匹配性質進行分析與量測。本文關注LDMOSFET之精準度，藉由一些量測數據以預測元件操作時之非匹配行為，並利用統計的方式分析物理造成的因素與元件製程技術非匹配的關係。

High Power metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely applied to power electronics owing to great semiconductor industry. In order to integrate power devices with planar IC process, the devices’ structure must be changed from the traditional vertical structure to lateral design, such that they can be integrated in the same chip. We can make the operation principle inside LDMOSFET clearly by performing the TCAD simulation. Finally, we use software simulation to obtain the details of mismatch characteristics under different situations. Careful tuning is made to obtain the optimum results.

The impact of device mismatch becomes more important because the dimensions of the devices are reduced. The matching properties of the threshold voltage, saturation current, and conductance of the device have been analyzed and measured. This thesis is concerned with the analyzable precision for LDMOSFET, and predicts the mismatch behavior of devices over a wide operating range using a set of measured data. Statistical methods are used to analyze physical causes that relate the mismatch to the process technologies.

                                                      頁次
中文摘要……………………………………………………………Ⅰ
英文摘要……………………………………………………………Ⅱ
誌謝    ……………………………………………………………Ⅲ
目錄    ……………………………………………………………Ⅴ
表目錄  ……………………………………………………………VIII
圖目錄  ……………………………………………………………IX

第一章 緒論
    1.1  研究背景................................    1
    1.2  研究目的與..............................    1
    1.3  研究流程及架構..........................    2

第二章 元件之發展與理論探討
    2.1  元件回顧.....................................5
        2.1.1      低摻雜汲極高壓金氧半電晶體.........5
        2.1.2      LDMOSFET 之發展....................5
    2.2  LDMOSFET 之基本結構..........................6
    2.3  LDMOSFET 之原理..............................7
        2.3.1      崩潰機制...........................7
        2.3.2      LDMOSFET 的導通電阻................10
        2.3.3  LDMOS 之操作原理.......................10
        2.3.4      RESURF原理.........................11
    2.4  LDMOSFET 之改良..............................12
        2.4.1  P 型場環體結構（P field ring）.........12
        2.4.2      多層阻值之漂移區...................13
    2.5  元件參數萃取.................................13
        2.5.1      串聯電組（RSD）之萃取模型..........13
        2.5.2      最小平方法之線性回歸...............16

第三章 元件特性與非匹配分析
    3.1  元件電性參數之定義...........................29
        3.1.1      崩潰電壓...........................29
        3.1.2      導通電阻（On Resistance）..........29
        3.1.3      啟始電壓（Threshold Voltage）......30
         3.1.4 飽和電流（Saturation Current）.........30
    3.2  對稱型LDMOSFET之製程步驟.....................31
    3.3  非匹配特性之量測.............................32
        3.3.1      非匹配特性萃取方式.................33
        3.3.2      非匹配之量測系統...................33
    3.4  元件非匹配之原理.............................34
    3.5  元件電性非匹配特性...........................37
    3.6  電性參數機率統計理論.........................41

第四章 元件非匹配之溫度效應
    4.1  啟始電壓受溫度之影響.........................56
    4.2  次臨限電流（Subthreshold Current.............59
    4.3  啟始電壓之非匹配度與溫度的關係...............61
    4.4  飽和電流受溫度之影響.........................64
    4.5  飽和電流之非匹配度與溫度的關係...............67
    4.6  電導受溫度之影響.............................68
    4.7  電導之非匹配度與溫度的關係...................69
    4.8  溫度效應之電性參數實際量測分析...............70

第五章 元件非匹配效應之結果與討論
    5.1  匹配度指標之定義.............................88
    5.2  元件非匹配度之模擬...........................88
    5.3  元件串聯電阻之非匹配量測.....................91
    5.4  飽和電流非匹配效應受參數之影響...............92
    5.5  非匹配度之分析...............................93
        5.5.1  基底電壓之效應.........................94
        5.5.2      閘極電壓之效應.....................95
        5.5.3      閘極氧化層厚度之效應...............95
        5.5.4      通道摻雜濃度之效應.................96
    5.6  製程步驟與匹配度之關連性.....................97
        5.6.1      結構一.............................97
        5.6.2      結構二.............................97
        5.6.3      結構三與不同結構間之比較...........98

第六章 結論...........................................132

參考文獻..............................................134

                                

[1] Robert W. Bower, Hans G. Dill, Kenneth G. Aubuchon, and Stephen A. Thompson, “MOS field effect transistors formed by gate masked ion implantation”, IEEE Trans. Electron Device, Vol.15, Issue 10, pp.757-761, 1968.

[2] Min Liu, C. A. T. Salama, P. Schvan and M. King, “A fully resurfed, BiCMOS-compatible, high voltage MOS transistor”, ISPSD, pp. 143-146, 1996.

[3] B. Jayant Baliga, “Power semiconductor Devices”, Boston, PWS, 1996.

[4] J. A. Appels and H. M. J. Vaes, “High voltage thin layer devices (RESURF devices)”, IEDM, Vol. 25, pp. 238-239, 1979.

[5] Min Liu, C. A. T. Salama, P. Schvan and M. King, “A fully resurfed, BiCMOS-compatible, high voltage MOS transistor”, ISPSD, pp. 143-146, 1996.

[6] J. G. Mena, and C. A. T. Salama, “High-voltage multiple-resistivity drift-region LDMOS”, Energy, Vol. 20, pp. 1313-1314, 1995.

[7] K. K. Ng and W. T. Lynch, “Analysis of the gate-voltage-dependent series resistance of MOSFET's”, IEEE Trans. Electron Devices, Vol. 33, Issue 7, pp.965-972, 1986.

[8] Bajolet A., Clerc R., “Low-Frequency Series-Resistance Analytical Modeling of Three-Dimensional Metal–Insulator–Metal Capacitors”, IEEE Trans. Electron Devices, Vol. 54, Issue 4, pp.742-751, 2007.

[9] Dieter K. Schroder, “Semiconductor material and device characterization”, Canada, Wiley, 1998.

[10] Wang Y., Cheung K. P., “Accurate Series-Resistance Extraction From Capacitor Using Time Domain Reflectometry”, IEEE Electron Device Letters, Vol. 28, Issue 4, pp.279-281, 2007.

[11] F.J. Garcfa Sanchez, A. Ortiz-Conde, “Series resistance and effective effective gate length extraction on short-channel PMOS device at liquid nitrogen temperature”, Proc. IEEE Int. Conf. on Micro. Test Structures, Vol. 7, pp.190-194,1994

[12] Xiao J. Z., “Knowledge bounded least squares method for the identification of fuzzy systems”, IEEE Trans. Systems, Vol. 33, Issue 1, pp.24-32, 2003.

[13] Stephen H. Friedberg, “Linear algebra”, New Jersey, Prentice Hall, 2003.

[14] S. Y. Han, H. W. Kim, S. K. Chung, “Surface field distribution and breakdown voltage of RESURF LDMOSFETs”, Microelectronics Journal, Vol. 31, pp.685-688, 2000.

[15] M. Koyanagi, T. Shimatani, “Evaluation of Self-Heating Effect in Poly-Si TFT Using Quasi Three-Dimensional Temperature Analysis”, IEDM, pp. 521-524, 1993.

[16] KADABA R. L., “Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design”, IEEE Journal of Solid-State Circuits, Vol. 21, Issue 6, pp. 1057-1066, 1986.

[17] MARCEL J. M. PELGROM, “Matching Properties of MOS Transistors”, IEEE Journal of Solid-State Circuits, Vol. 24, Issue 5, pp. 1433-1441, 1989.

[18] Patrick G. Drennan, “Understanding MOSFET Mismatch for Analog Design”, IEEE Journal of Solid-State Circuits, Vol. 38, Issue 3, pp. 450-457, 2003.

[19] JYN-13ANG SHYU, GABOR C. TEMES, “Random Error Effects in Matched MOS Capacitors and Current Sources”, IEEE Journal of Solid-State Circuits, Vol. 19, Issue 6, pp. 948-955, 1984.

[20] Yong Hae K., “High-performance ultralow-temperature polycrystalline silicon TFT using sequential lateral solidification”, IEEE Electron Device Letters, Vol. 25, Issue 8, pp.550-552, 2004.

[21] Bajolet A., Clerc R., “Reliability governed by the relative locations of random variables following a homogeneous Poisson Process in a finite domain”, IEEE Trans. Reliability, Vol. 53, Issue 2, pp.226-237, 2004.

[22] S.M. Sze., “Semiconductor devices physics and technology”, New York, Wiley, 2002.

[23] Gary M. Dolny, Gerald E. Nostrand, and Kevin E. Hill “The Effect of Temperature on Lateral DMOS Transistors in a Power IC Technology” IEEE Trans. Electron Devices, Vol.39, Issue 4, pp. 990-995, 1992.

[24] G. Baccarini, A. M. Mazzoni, and C. Morandi, “The diffuse scattering model of effective mobility in the strongly inverted layer of MOS transistors”, IEEE Journal of Solid-State Circuits, Vol.17, Issue 9, pp. 785-788, 1974.

[25] Gustin, C., Mercha, A., “Stochastic Matching Properties of FinFETs”, IEEE Electron Device Letters, Vol. 27, Issue 10, pp.846-848, 2006.

[26] Yuanzhang Sun, “Influence of transfer conductance on power system stability with excitation control”, Power Engineering Society General Meeting, IEEE, pp.1-6, 2006.

[27] James D. Plummer, Michael D. Deal, Peter B. Griffin, “Silicon VLSI technology”, New Jersey, Prentice Hall, 2002.

[28] Abelein U., Born M., “Improved Reliability by Reduction of Hot-Electron Damage in the Vertical Impact-Ionization MOSFET (I-MOS)”, IEEE Electron Device Letters, Vol. 28, Issue 1, pp.65-67, 2007.

[29] Saeed .G, “Fundamentals of probability”, New Jersey, Prentice Hall, 2000.

[30] Dahlstrom M., Walter K, “Influence of the Ge profile on VBE and current gain mismatch in Advanced SiGe BICMOS NPN HBT with 200 GHz fT”, Bipolar/BiCMOS Circuits and Technology Meeting, 2006, pp.1-4, 2006.

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文