隨著晶片設計的發展，工程師對於晶片的效能要求也越來越高，因此出現了小晶片這項技術，它可以在提高晶片效能的同時控制生產成本。然而，這項技術雖然可以替晶片設計帶來很大的優點，但它仍然有一些安全性方面的問題需要解決。其中一個最大的問題是會擔心有攻擊者去惡意的引入間諜小晶片這類的惡意電路，並且透過匯流排竊取裸晶之間傳輸的重要資料，這樣的話會對系統的機密性造成很大的威脅。在這個工作中，我們提出了一項框架，透過多層的保護機制去保護裸晶和裸晶之間所傳輸的數據。此外，和其他類似的工作相比，我們的方法在效率、硬體開銷方面所造成負擔更小。

With the advancement of chip design, engineers' performance requirements for chips are also increasing. Thus, the technology of chiplets has emerged, which can enhance chip performance while controlling production costs. However, although this technology offers significant advantages for chip design, it still has some security issues that must be addressed. One of the biggest concerns is that attackers might maliciously introduce spy chiplets or similar malicious circuits, which could intercept critical data transmitted between dies via the bus. This poses a significant threat to the system's confidentiality. In this work, we propose a framework that protects data transmitted between dies through a multi-layer protection mechanism. Additionally, compared to other similar works, our methodology has better performance in terms of efficiency and hardware overhead.

[1] J. Knechtel, S. Patnaik, and O. Sinanoglu, “Protect your chip design intellectual property: An overview”, Proc. of Int’l Conf. on OmniLayer Intelligent System, pp. 211-216, 2019.
[2] J. J. Rajendran, O. Sinanoglu, and R. Karri, “Building trustworthy systems using untrusted components: A high-level synthesis approach”, Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 9, pp. 2946-2959, Sep. 2016.
[3] M. Nabeel, M. Ashraf, S. Patnaik, V. Soteriou, O. Sinanoglu and J. Knechtel, “2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets”, IEEE Transactions on Computers, Vol. 69, No. 11, pp. 1611-1625, Nov. 2020.
[4] A. Sayed-Ahmed, J. Haj-Yahya, and A. Chattopadhyay, “SoCINT: Resilient System-on-Chip via Dynamic Intrusion Detection”, Proc. of Int’l Conf. on VLSI Design and Int’l Conf. on Embedded Systems, pp. 359-364, 2019.
[5] C. Dong, G. He, X. Liu, Y. Yang, and W. Guo, “A Multi-Layer Hardware Trojan Protection Framework for IoT Chips”, IEEE Access, Vol. 7, pp. 23628-23639, 2019.
[6] N. Fern, I. San, C. K. Koc, and K. -T. T. Cheng, “Hiding Hardware Trojan Communication Channels in Partially Specified SoC Bus Functionality”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 9, pp. 1435-1444, Sept. 2017.
[7] K. M. Alatoun, S. M. Achyutha, and R. Vemuri, “Efficient Methods for SoC Trust Validation Using Information Flow Verification”, Proc. of IEEE Int’l Conf. on Computer Design, pp. 608-616, 2021.
[8] N. Vashistha, M. M. Al Hasan, N. Asadizanjani, F. Rahman, and M. Tehranipoor, “Trust Validation of Chiplets using a Physical Inspection based Certification Authority”, Proc. of IEEE Electronic Components and Technology Conf., pp. 2311-2320, 2022.
[9] E. M. Benhani, C. M. Lopez, and L. Bossuet, “Secure Internal Communication of a Trustzone-Enabled Heterogeneous Soc Lightweight Encryption”, Proc. of IEEE Int’l Conf. on Field-Programmable Technology, pp. 239-242, 2019.
[10] S. Janakiraman, K. S. Sree, V. L. Manasa, S. Rajagopalan, K. Thenmozhi, and R. Amirtharajan, “On the Diffusion of Lightweight Image Encryption in Embedded Hardware”, Proc. of IEEE Int’l Conf. on Computer Communication and Informatics, pp. 1-6, 2018.
[11] S. Suchit and K. Suneja, “Implementation of Secure Communication System Using Chaotic Masking”, Proc. of IEEE Global Conf. on Computing, Power and Communication Technologies (GlobConPT), pp. 1-5, 2022.
[12] N. Abbassi, M. Gafsi, M. A. Hajjaji, and A. Mtibaa, “Hardware design and implementation of a lightweight stream-cipher cryptosystem: A Chaotic/Reversible Cellular Automata Approach”, Proc. of IEEE Int’l Conf. on Sciences and Techniques of Automatic Control and Computer Engineering, pp. 255-260, 2022.
[13] S. Kostoudas, O. Markovskyi, N. Doukas, and N. Bardis, “Secure and Encrypted Communication System on Mobile Devices”, Proc. of IEEE Int’l Conf. on Dependable Systems, Services and Technologies, pp. 1-6, 2022.
[14] S. Bauer, M. Brunner, and P. Schartner, “Lightweight Authentication for Low-End Control Units with Hardware Based Individual Keys”, Proc. of IEEE Int’l Conf. on Robotic Computing, pp. 425-426, 2019.
[15] R. Anusha, P. R. Rao, and N. P. Rai, “Secured authentication of RFID devices using lightweight block ciphers on FPGA platforms”, IEEE Access, Vol. 11, pp. 107472-107479, 2023.
[16] I. Cetintav and M. T. Sandikkaya, “LAKE: A Low-cost, Lightweight Authentication, Key Exchange, and Data Transfer Scheme for IoT”, Proc. of Mediterranean Conf. on Embedded Computing, pp. 1-4, 2023.
[17] S. B. Suhaili, C. C. A. Niam, Z. M. Zain, and N. Julai, “Design and Implementation of MD5 Hash Function Algorithm Using Verilog HDL”, Proc. of National Technical Seminar on Unmanned System Technology 2020, Lecture Notes in Electrical Engineering, Vol. 770, pp. 499-510, 2022.
[18] V. R. Andem, "A Cryptanalysis of the Tiny Encryption Algorithm", Ph.D. Dissertation, The University of Alabama, Jan. 2003.
[19] H. -Y. Chi, K. -J. Lee, and T. -C. Jao, “Lightweight Hardware-Based Memory Protection Mechanism on IoT Processors”, Proc. of IEEE Asian Test Symposium, pp. 13-18, 2021.
[20] C.-C. Wu, M.-H. Kuo, and K.-J. Lee, “A dynamic-key secure scan structure against scan-based side channel and memory cold boot attacks”, Proc. Asian Test Symp., pp. 48-53, 2018.
[21] Syntacore. SCR1. Accessed: 2024. [Online]. Available: https://github.com/syntacore/scr1.
[22] Alexforencich. Verilog-AXI. Accessed: 2024. [Online]. Available: https://github.com/alexforencich/verilog-axi.
[23] ultraembedded. core_soc. Accessed: 2024. [Online]. Available: https://github.com/ultraembedded/core_soc.
[24] mematrix. AES-FPGA. Accessed: 2024. [Online]. Available: https://github.com/mematrix/AES-FPGA.
[25] AlexeyShashkov. RSA. Accessed: 2024. [Online]. Available: https://github.com/AlexeyShashkov/RSA.
[26] secworks. md5. Accessed: 2024. [Online]. Available: https://github.com/secworks/md5.