未來由物聯網和無線感測網路系統所產生的大數據時代中，雲端運算將會需要大量的資料傳輸和複雜的資料運算，而且有待機時間長的特性和低耗能的需求，為了能夠節省大量資料傳輸的耗能，通常都會使用一個過濾器，內部搭載一個三元內容循址儲存器於各種平台介面之間，此三元內容循址記憶體可先將接收到的資料進行快速的比對和過濾，將不需要傳輸到雲端的資料過濾掉，僅傳輸需要傳輸的資料，如此就能大幅減少資料傳輸的耗能，以達到節省能源的效用。
傳統以靜態隨機存取記憶體為基底的三元內容循址記憶體需要兩組靜態隨機存取記憶體來儲存三種資料(1/0/X)，然而此靜態隨機存取記憶體為基底的三元內容循址記憶體為16顆電晶體所組成的記憶胞，使得系統在面積有限的情況下，傳統靜態隨機存取記憶體為基底的三元內容循址記憶體的容量小；此外隨著製程的微縮，靜態隨機存取記憶體為基底的三元內容循址記憶體其待機漏電的耗能將大幅增加，一般解決待機漏電耗能的方法是待機時將資料搬動到另外一個非揮發性記憶體巨集內儲存起來，然而此雙巨集的方法不但開關機所需要搬動資料的耗能大，且受限於傳輸介面的輸入輸出端數，導致開關機時資料搬動的時間和耗能隨著容量的增加而變得更為嚴重。
此研究將結合高密度、高低阻態比值大的非揮發性記憶體元件－電阻式記憶體和電晶體所組成的非揮發性三元內容循址儲存器，將可以解決傳統靜態隨機存取記憶體為基底的三元內容循址記憶體其待機漏電的耗能，並且在相同容量下能夠有更小的面積，而此單一巨集的非揮發性三元內容遁址記憶體更能加速開關機的速度且可以節省開關機時資料搬動的耗能。此次研究目標除了研發新的非揮發性三元內容遁址記憶體其記憶胞外，更要突破近年來國際論文所發表的非揮發性三元內容遁址記憶體所遇到的問題，達到比先前架構更小的記憶胞面積、更快的搜尋速度和更低的非揮發性記憶體元件改寫所需耗能，且要能解決先前架構配對線長度受限制的瓶頸。
本研究提出一雙向分壓控制之3T1R非揮發性三元內容循址記憶體，於記憶胞層級結合電阻式記憶體元件與電晶體，達到
1. 為傳統以靜態隨機存取記憶體為基底的三元內容循址記憶體(16顆電晶體)面積的1/5倍，即同樣面積條件下可達到5倍的容量。
2. 解決待機漏電耗能問題，並可直接關機、開機只需等待周邊邏輯電路恢復功能，達到快速、低耗能開關機特色。
3. 改寫非揮發性記憶體元件所需要的總耗能比先前記憶胞中使用兩個非揮發性記憶體元件架構還要降低1.33倍。
實體晶片巨集大小為4千位元且量測到搜尋時間為0.96奈秒，是目前國際所有發表的非揮發性三元內容遁址記憶體中最快的量測數據。

The development of embedded systems and wireless technology has led to a wide range of applications; however, the storage of data associated with these applications presents serious difficulties, particularly when dealing with long standby time and discontinuous power supply. This has led to the development of cloud servers and databases; however the transmission of invalid data between the cloud and local devices plays a major role in overall power consumption. By implementing a filter capable of identifying the input data, devices can reduce the amount of data that must be sent to the cloud, and further reduce the overall power consumption.
TCAM is meant to address the needs for more speed and large storage. However, for the feature of normally-off, we need the Nonvolatile Memory to reduce large standby power companying with large storage. The implementation of non-volatile memory in TCAM generally involves a 2-macro solution, which includes a SRAM-based TCAM macro with a nonvolatile memory macro, such as flash. In power-off mode, the TCAM macro stores data within a nonvolatile memory macro. In power-on mode, the data is restored from the nonvolatile memory macro. Unfortunately, limited I/O bandwidth can produce large delays and induce large energy consumption associated with the movement of data in power-on and power-off operations.
This study developed a single macro solution, which is capable of reducing area overhead, minimizing store/restore energy, and speeding up store/restore operations. The proposed method does not require the movement of data and enables immediate power-on/off switching, based on the fact that only logic-based peripheral circuits need to be woken up..
　　This study proposed a bi-directional voltage divider control (BVDC) 3T1R nonvolatile TCAM (nvTCAM) which can reach:
1. 1/5 times smaller than traditional 16T SRAM-based TCAM, and 5 times larger capacity with same area.
2. Fast and low power wake-up and backup operations.
3. 1.33 times smaller NVM device write energy than other 2R-based nvTCAM.
The capacity of implemented macro is 4kbits, and 0.96ns search time is achieved. The measured search speed is the most fast one compared with other published nvTCAM.

[1] C.-J. Cheng, et al., “A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, Issue 5, pp. 841-854, May 2012.
[2] Harvard sensor network lab, Harvard College. 2008. CodeBlue: Wireless Sensors for Medical Care. Available at: http://fiji.eecs.harvard.edu/CodeBlue
[3] Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update 2014–2019 White Paper. Available at: http://www.cisco.com/c/en/us/solutions/collateral/service-provider/visual-networking-index-vni/white_paper_c11-520862.html
[4] K. Nii, et al., “A 28nm 400MHz 4-Parallel 1.6Gsearch/s 80Mb Ternary CAM," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 240-241, Feb 2014.
[5] J. Tsouhlarakis, et al., “A flash memory technology with quasi-virtual ground array for low-cost embedded applications,” IEEE Journal of Solid-State Circuits (JSSC), vol. 36, no. 6, pp. 969–978, Jun. 2001.
[6] M.-F. Chang, et al., “A process variation tolerant embedded split-gate Flash memory using pre-stable current sensing scheme,” IEEE Journal of Solid-State Circuits (JSSC), vol. 44, no. 3, pp.987-994, March 2009.
[7] S. Hanzawa, et al., “A 512kB embedded Phase Change Memory with 416kB/s write through at 100uA cell write current,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 474-475, Feb. 2007.
[8] G. D. Sandre, et al., “A 90nm 4Mb embedded Phase-Change memory with 1.2V 12ns read access time and 1MB/s write throughput”, IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 268-269, Feb. 2010.
[9] Y.-N. Hwang, et al., “MLC PRAM with SLC write-speed and robust read scheme,” Symposium on VLSI Circuits (VLSIC) Dig. Tech. Papers, pp. 201-202, June 2010.
[10] Y. Choi, et al., “A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 46-48, Feb. 2012.
[11] M. Durlam, et al., “A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects,” IEEE Journal of Solid-State Circuits (JSSC), vol. 38, no. 5, pp. 769-773, May 2003.
[12] Y. Iwata, et al., “A 16Mb MRAM with FORK Writing Scheme and Burst Modes”, IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp.138-139, Feb. 2006.
[13] K. Tsuchida, et al., “A 64Mb MRAM with Clamped-Reference and Adequate-Reference Schemes,“ IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 258-259, Feb. 2010.
[14] S. Dietrich, et al., “A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control,” IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 4, pp. 839-845, April 2007.
[15] C.-J. Chevallier, et al., “A 0.13μm 64Mb Multi-Layered Conductive Metal-Oxide Memory,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 260−261, Feb. 2010.
[16] S.-S. Sheu, et al., “Fast-Write Resistive RAM (RRAM) for Embedded Applications,” IEEE Design and Test of Computers, vol. 28. no. 1, pp. 64-71, Jan. 2011.
[17] S.-S. Sheu, et al., “A 4Mb Embedded SLC Resistive-RAM Macro with 7.2ns Read-Write Random-Access Time and 160ns MLC-Access Capability,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 200−201, Feb. 2011.
[18] W. Otsuka, et. al., “A 4Mb Conductive-Bridge Resistive Memory with 2.3GB/s Read-Throughput and 216MB/s Program-Throughput,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 210-211, Feb. 2011.
[19] A. Kawahara, et al. “An 8Mb Multi-Layered Cross-Point ReRAM Macro with 443MB/s Write Throughput,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 432-433, Feb. 2012.
[20] M.-F. Chang, et al., “A 0.5V 4Mb Logic-Process Compatible Embedded Resistive RAM (ReRAM) in 65nm CMOS Using Low Voltage Current-Mode Sensing Scheme with 45ns Random Read Time," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 434-435, Feb. 2012.
[21] X.-Y. Xue, et al., “A 0.13μm 8Mb Logic Based CuxSiyO Resistive Memory with Self-Adaptive Yield Enhancement and Operation Power Reduction,” IEEE Symposium on VLSI Circuits (VLSIC) Dig. Tech. Papers, pp. 42-49, 2012.
[22] M.-J. Lee, et al., “2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications,” IEEE International Electron Devices Meeting (IEDM), pp. 771-774, Dec. 2007.
[23] C. Cagli, et al., “Evidence for threshold switching in the set process of NiO-based RRAM and physical modeling for set, reset, retention and disturb prediction,” IEEE International Electron Devices Meeting (IEDM), pp. 1-4, 15-17 Dec. 2008.
[24] U. Russo, et al., “Self-Accelerated Thermal Dissolution Model for Reset Programming in Unipolar Resistive-Switching Memory (RRAM) Devices,” IEEE Transactions on Electron Devices, Vol. 56, Issue 2, pp. 193-200, Feb. 2009
[25] S.-S. Sheu, P.-F Chiu, et al., “A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme,” IEEE Symposium on VLSI Circuits (VLSIC Dig. Tech. Papers), June 2009.
[26] H.-Y. Lee, et al., “Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM,” IEEE International Electron Devices Meeting (IEDM), pp. 1-4, Dec. 2008.
[27] H.-Y. Lee, et al., “Comprehensively study of read disturb immunity and optimal read scheme for high speed HfOx based RRAM with a Ti layer,” International Symposium on VLSI Technology Systems and Applications (VLSI-TSA), pp. 132-133, April 2010.
[28] J. Li, et al., “1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, Issue 4, pp. 896-907, April 2014.
[29] S. Matsunaga, et al., “A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture,” Symposium on VLSI Circuits (VLSIC) Dig. Tech. Papers, pp. 44-45, June 2012.
[30] L.-Y. Huang, et al., “ReRAM-based 4T2R Nonvolatile TCAM with 7x NVM-Stress Reduction, and 4x Improvement in Speed-WordLength-Capacity for Normally-Off Instant-On Filter-Based Search Engines Used in Big-Data Processing,” Symposium on VLSI Circuits (VLSIC) Dig. Tech. Papers, pp. 122-123, June 2014.
[31] M.-F. Chang, C.-C. Lin, et al., “A 3T1R Nonvolatile TCAM Using MLC ReRAM with Sub-1ns Search Time,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 318-319, Feb. 2015.