Recently, portable devices play an important role in human life. Embedded systems in these devices become more complex and have higher requirements. In the embedded systems, high performance and low power consumption are the most critical issues. The expandable cache [2], therefore, is proposed to effectively reduce the miss rate and power consumption with a small amount of area overhead. Nevertheless, in the expandable cache, using only the most significant bit (MSB) may suffer from the thrashing problems. In this thesis, we
introduce a new cache design based on the expandable cache using the data life time concept to find the best expansion scheme for different applications and at different program stages. Our new cache design can provide flexible expansion schemes by using more bits and change the configuration dynamically by the instructions inserted into the program at compile time. The experimental results show that our new cache design with 2% static instruction overhead can reduce 37.05% miss rate and 13.58% power consumption, in average, as compared with the direct-mapped cache.

隨著裝載各種嵌入式系統的可攜式產品變的越來越流行，嵌入式系統也變的越來越複雜，人們的要求也越來越高。小到電子體溫計，大到飛行導航器都是嵌入式系統能夠應用的地方。
目前嵌入式系統最重要的目標是高效能和低電耗。可擴大快取[2]，增加少部份的硬體空間卻能有效的提高效率及降低電力消耗。然而，可擴大快取只使用了最高的位元當做找到第二個存放位置的判斷依據，這樣還是會造成相當比例的執行時間在記憶體及快取間搬移資料。
在這篇論文中，我們根據可擴大快取做一些少部份的修正提出一個新的快取架構並搭配軟體來控制我們所新增的硬體。軟體部份，利用資料生存時間的概念來分析程式架構並分析出在不同應用程式和不同程式階段中最適合的擴大機制。
我們這個新的架構提供彈性的擴大機制而且可以藉著在編譯時插入指令來動態的改變機制。我們的實驗結果顯示我們在增加2%以下的靜態指令平均可以比一般的直接應對的快取提高37.05%的效能及降低13.58%的電力消耗。

[1] L. Lee, S. Kannan, and J. Fridman, “MPEG4 Video Codec on a Wireless Handset Baseband Syatem”,In Proc. Workshop Media and Signal Processors fir Embedded Systems and SOCs, 2004.
[2] G. Bournoutian and A. Orailoglu, “Miss Reduciton in Embedded Processors Through Dynamic, Power-Friendly Cache Design”, Design Automation Conference, pp. 304-309,June, 2008.
[3] J. Kin, M. Gupta, and W. H. Mangione-Smith, “The Filter Cache: An Energy efficient memory structure,”30th International Symposiun on Microarchitecture, pp. 184-193,1997.
[4] D. H. Albonesi, “Selective Cache Ways: On-demand Cache Resource Allocation,”32th International Symposium on Microarchitecture, pp. 248-259, 1999.
[5] A. Gonzalez, C. Aliagas, and M. Valero, “A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality,” 9th International Conference on Supercomputing, pp. 338-347, 1995.
[6] P. Petrov and A. Orailoglu, “Performance and Power Effectiveness in Embedded Processors - Customizable Partitioned Caches,”IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1309- 1318, 2001.
[7] N. P. Jouppi, “Improving Direct-mapped Cache Performance by the Addition of Small Fully-Associatve Cache and Prefetch Buffers,”SIGARCH Computer Architecture News, pp. 364-373, 1990.
[8] A. Agarwal and S. D. Pudar, “Column-Associative Caches: a Techniques for Reducing
the Miss Rate of Direct-Mapped Caches,” SIGARCHI Computer Architecture News, pp.179-190, 1993.
[9] A. Malik, B. Moyer and D. Cermak, “A Lower Power Unified Cache Architecture Providing
Power and Performance Flexibility,” International Symposium on Low Power Electronics and Designs, 2000.
[10] SPEC CPU2000 Benchmarks, http://www.spec.org/cpu/.
[11] D. C. Burger, T. M. Austin and S. Bennett, “Evaluating Future MicroprocessorsVThe SimpleScalar Tool Set,” Technical Report 1342, University of Wisconsin-Madison, CS Department, June 1997.
[12] S. J. Wilton, N. P. Jouppi, “CACTI: An Enhanced Cache Access and Cycle Time Model,” IEEE Journal on Solid-State Circuits, 31(5): pp. 677-688, 1996.
[13] J. T. Robinson and M. V. Devarakonda, “Data Cache Management using Frequency Based Replacement,” SIGMETRICS, pp.134-142, 1990