摘要
近年來，越來越多關於在互補式金氧半電晶體(CMOS)邏輯製程上製作雙極性電晶體(BJT)的研究被發表。互補式金氧半電晶體有製造密度高，省電的優點，而雙極性電晶體則可以提供高速，高電流驅動力以及低雜訊的能力，但是相對的需要較大的耗電。 在同一個晶片設計上結合金氧半電晶體和雙極性電晶體兩種技術，電路設計工程師可以在省電和高效能之間作最佳化的選擇，讓晶片設計的效能超過只用單一種電晶體的設計。大部份現存的互補式金氧半電晶體製程(BiCMOS)是使用高效能的客製化垂直雙極性電晶體。但是金氧半電晶體和雙極性電晶體在製作上的不相容，會使得製程變的昂貴且複雜。
在本論文中，提出一個可以適用於射頻、高速數位/類比電路設計的低成本、低雜訊、高增益、高頻率，且完全不需要額外光罩的新型邏輯相容垂直雙極性電晶體(logic compatible vertical bipolar junction transistor)，並且其高頻、高增益特性，已經在台積電0.18微米邏輯製程上被驗證。
論文中提出的新型邏輯相容垂直雙極性電晶體，有主要兩種結構，分別為RPO對準與閘極自我對準結構。閘極自我對準結構，類似兩個並聯的N型或是P型金氧半電晶體，利用源極和集極的自我對準結構來區隔射極(Emitter)以及基極(Base)。而RPO對準結構則類似閘極自我對準結構去掉閘極。兩種結構的射極和基極都是利用反態LDD和Pocket去製作。
RPO對準結構的截止頻率可以達到17.5GHZ，最大功率頻率15.5GHZ，電流增益超過60。而閘極自我對準結構，在90nm的模擬當中，更可以達到45GHZ，電流增益超過70。更多相關的電晶體電性將會在論文中討論。

Abstract
Recently there are a lot of studies and researches in bipolar junction transistor (BJT) technology with fully CMOS logic compatible process. CMOS technology is known applied for low standby power dissipation, high packing density, and easy processes. However, bipolar junction transistor (BJT) technology is able to provide higher switching speed, current drivability, and low-noise performance, in spite of consuming more power. To combine the two technologies is the superior solution for the IC design, i.e. the designers can therefore obtain the lower power dissipation and noise level but increase the circuit speed and performance in some cases. Currently, most BiCMOS (BJT plus CMOS) technologies must utilize high performance but complicate Vertical BJTs in CMOS process platform. This kind of combination will produce a lot of extra masking steps and very complicate process flow, the benefit of CMOS and BJT will be significantly declined owing to high cost and low yield concerns.
A new high frequency logic compatible Vertical Bipolar Junction Transistor without any extra masks has been proposed in this paper. The new structure has low cost and CMOS logic compatible properties, and still remains the advantages of BJT in high switching speed, low noise, and high gain. The device and its high frequency measurement patterns have been fabricated and demonstrated by TSMC 0.18um logic process and fully characterized by this study.
The new logic compatible vertical bipolar junction transistors include two kinds of the layout structures: RPO Align (RPOA) and Gate Self-Align (GSA) structure. The gate self-align structure consists of two parallel poly-Si gates for separating emitter and base regions, the following self-aligned implantation can easily form the emitter, base, and collectors without additional masks or process steps. A RPO align structure is similar to the previous Gate self-align structure but use RPO layer instead of poly gate formation. The structure is not suitable for self-aligned implantation for emitter and base formation but use the anti-LDD and anti-pocket implantations to define the emitter and base regions.
The RPO Align BJT (RA-BJT) can achieve a current gain over 60 and 17.5/15.5 GHz for the fT/fmax. Moreover, the Gate Self-Aligned BJT (GSA-BJT) also can achieve a high current gain over 70 and 45 GHz for the fT/fmax according to the simulation of TSMC’s 90nm CMOS logic process. More comprehensive characteristics will be exhibited and in the papers.

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