在IC設計中，有一些modules是包含著有input/output connections，如果我們在floorplan時，便將這些含有input/output connections的modules放置到IC chip的四個邊邊上，如此一來，便可以減少這些modules連接到input/output pads的wires。換句話說，就可以減少繞線(routing)所要花的時間，也減少了所需要繞的線的數目。
因此，我們將會使用Sequence Pair(一種non-slicing structure floorplan的表示方式)。藉由Sequence Pair的性質，找出一些脈絡，讓我們在尋求合法解的過程中，不會浪費時間找到非法的解，以減少尋求合法解的時間。

In this thesis, we will study the boundary constrained floorplanning problem. A floorplan can be classified as slicing or non-slicing structure based on the placement of modules. The floorplan based on non-slicing structure packs modules tighter than floorplan based on slicing structure. Recently, some non-structure representations were proposed. One of these representations is Sequence Pair. Sequence Pair is a very compact representation and can represent all possible floorplan strucutres. In floorplanning, if modules with input/output connections are placed at boundary of the chip, it will save routing area and routing time. Besides, floorplanning is usually done hierarchically in which modules are grouped into different units. It will help if some modules are packed along the boundary of the unit so that they can be put in the neighboring. Therefore, we will focus on the boundary constrained modules placement problem using Sequence Pair representation. First, we will find some rules for Sequence Pair when boundary constraints are given. Based on these rules, we propose a algorithm that will always search solution in legal solution space.
In this way, a lot of time is saved due to the pruning of search space.

Our algorithm proceeds in two phases: Pos and Neg. Pos permutes the positive sequence using Simulated Annealing and Neg permutes the negative sequence exhaustively.At last, we will show our experimental results.

H. Murata, K. Fujiyoshi, S. Nakatake and Y. Kajitani,
"Rectangle-Packing-Based Module Placement,"
in Proc. of ICCAD, 1995, pp. 472-479.