鎖相迴路之高錯誤診斷率自我測試電路｜國立清華大學博碩士論文庫

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研究生：	林建翰 Chien-Han Lin
論文名稱：	鎖相迴路之高錯誤診斷率自我測試電路 High Fault Coverage Built In Self Test for PLLs
指導教授：	張慶元 Tsin-Yuan Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	65
中文關鍵詞：	鎖相迴路、自我測試
外文關鍵詞：	PLL, BIST
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這篇論文主要討論一個鎖相迴路的高錯誤偵測率自我測試電路。在現今的趨勢中，鎖相迴路是相當重要的應用，舉凡低抖動的頻率合成器、時脈恢復與同步器等。對一個鎖相迴路來說，當電路表現不符預期時，找出錯誤區塊對於提升產能與降低成本有相當重要的幫助。與數位積體電路設計領域不同的是，結構性測試例如掃描測試與內建式自我測試已經有相當普遍的應用，在混合式積體電路中，諸如此類的應用依然發展未成熟。也就是說，雖然內建式自我測試在數位積體電路中已經有很廣泛的應用層面，混合式積體電路的設計者依然還再尋找一個適當的解決方案。在這篇論文中，提供一個內建式自我測試電路方法來做錯誤診斷。但是在鎖相迴路電路中，結構上的錯誤可能發生在鎖相迴路中任意一個區塊，包括電壓控制震盪器，除頻器，低通濾波器，相位頻率偵測器和充放電幫浦。在內建式的自我測試電路中，是利用已經存在的元件來做錯誤測試和量測。主要的想法是增加一些基本的電路邏輯元件來做為強健的電路，目的是可以提高錯誤診斷率，也很容易觀察其輸出結果，和增加可靠性。在這篇論文中的內建式自我測試電路是利用台積電0.18毫米的CMOS製程來做模擬，可以提高錯誤診斷率到99.72%。

ABSTRACT This thesis proposes a method for phase-locked loop detection. PLL plays a very important role in communication systems in present times, such as low-jitter PLL-based frequency synthesizer、clock recovery and synchronization. For the PLL, to improve the yield and achieve cost reduction, it is important to detect the faulty block when it does not meet the specifications as expected. Unlike in the domain of digital IC testing, where structural test methods such as scan-tests and build-in self testing (BIST) have become a common practice, testing of mixed-signal ICs in a structured way is still in its infancy. Thus is, an effective built-in self test (BIST) structure of a PLL in digital applications is presented in this thesis. In this thesis, a BIST approach is presented for locating structural fault model in PLL blocks including VCO, Divider-By-N block, Loop Filter, Phase Detector and Charge-Pump. By applying exiting elements of PLLs to test and measure, the proposed BIST circuit that is verified by the simulation in a 0.18um CMOS process has the advantages of small area overhead and 99.72% fault coverage.

Chapter 1 Introduction..................................14 1.1 Motivation......................................................................................................14 1.2 Previous Work................................................................................................16 1.3 Thesis Outline................................................................................................18 Chapter 2 PLL Design Overview..................19 2.1 Phase Frequency Detector (PFD) Design......................................................19 2.2 Voltage controlled oscillator (VCO) Design..................................................22 2.3 Charge-Pump design......................................................................................24 2.4 Divider Design...............................................................................................26 2.5 Whole PLL Design.........................................................................................29 Chapter 3 Propose Structure.........................33 3.1 Proposed Circuit Overview............................................................................33 3.2 Operations of proposed BIST........................................................................34 3.2.1 Normal Mode......................................................................................35 3.2.2 Test Mode............................................................................................36 3.2.2.1. Charge-Test Operation:..........................................................36 3.2.2.2. Discharge-Test Operation:......................................................37 3.3 Fault-Evaluation Circuit.................................................................................38
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3.4 Robust Circuit................................................................................................39 3.5 The Testing Procedure....................................................................................42 Chapter 4 Fault Model and Simulation.........45 4.1 Fault Models..................................................................................................45 4.1.1 Hard Faults..........................................................................................45 4.1.2 Soft Faults...........................................................................................47 4.2 Behavior Simulation Results..........................................................................47 4.3 Voltage Control Oscillation Fault Simulation................................................47 4.3.1 Summary.............................................................................................51 4.4 Loop Filter Fault Simulation..........................................................................52 4.5 Divider Fault Simulation................................................................................54 4.5.1 Summary.............................................................................................56 4.6 Charge-Pump Fault Simulation......................................................................57 4.6.1 Summary.............................................................................................59 4.7 Phase Detector Fault Simulation....................................................................60 4.7.1 Summary.............................................................................................62 Chapter 5 Conclusion and Future Work........63 5.1 Conclusion.....................................................................................................63 5.1 Future Work...................................................................................................64

                                

[1] S. Kim and M. Soma, “An all-digital built-in self-test for high-speed phase-locked loops,” IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol. 48, no. 2, pp. 141–150, Feb. 2001. [2] P. Goteti, G. Devarayanadurg, and M. Soma, “DFT for embedded charge-pump PLL systems incorporating IEEE 1149.1,” in IEEE Custom Integrated Circuits Conf., , pp. 210–213, 1997. [3] S. Sunter and A. Roy, “BIST for phase-locked loops in digital apin Proc. Int. Test Conf., pp. 532–540, Sep. 1999. [4] B. R. Veillette and G. W. Roberts, “On-chip measurement of the jitter transfer function of charge-pump phase-locked loops,” IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 483–491, Mar. 1998. [5] K. A. Jenkin and J. P. Eckhardt, “Measuring jitter and phase error in microprocessor phase-locked loops,” IEEE Design Test Comput., vol.17, no. 2, pp. 86–93, Apr.–Jun. 2000. [6] K. Arabi and B. Kaminska, “Oscillation Built-in Self Test (OBIST) scheme for functional and structural testing of analog and mixed-signal integrated circuits,” in Proc. Int. Test Conf., pp. 786–795, Nov. 1997. 66
[7] I. Rayane, J. V. Medina, and M. Nicolaidis, “A digital BIST for operational amplifiers embedded in mixed-signal circuits,” in IEEE VLSI Test Symp., pp. 304–310, Apr. 1999. [8] C. L. Hsu, Y. Lai, and S. W. Wang, “Built-In Self-Test for Phase-Locked Loops,” IEEE Trans.Instrum. Meas., vol. 54, no. 3, pp. 996-1002, June 2005. [9] J. G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE Journal of Solid-State Circuits, Vol.31, No.11, Nov. 1996. [10] J.Lee, B.Kim, “A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control”, IEEE Journal of Solid-State Circuits, Vol. 35, No.8, Aug 2000. [11] E.J.Hernandez, A.D.Sanchez, “Positive Feedback CMOS Charge-Pump Circuits for PLL Applications”, Proc. of the 44th IEEE Midwest Symposium on Circuits and Systems, Vol. 2, pp. 836 – 839, Aug. 2001.

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