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研究生: 湯皓雲
Hao-Yun Tang
論文名稱: 具有正交校正功能的互補式金屬氧化半導體次諧波升頻混頻器
A CMOS Quadrature Sub-Harmonic Up-Mixer with I/Q Calibration
指導教授: 柏振球
Jenn-Chyou Bor
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2007
畢業學年度: 96
語文別: 英文
論文頁數: 106
中文關鍵詞: 次諧波混頻器八相位產生器正交校正無線通訊
外文關鍵詞: Sub-harmonic, mixer, octet-phases generator, I/Q calibration, wireless communication
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  • 本論文提出一個正交升頻混頻電路,並且使用次諧波混頻技巧與正交校正電路來增進其效能,電路使用0.18微米金屬氧化半導體製程來實現並可用於3.5 GHz的直接升頻WiMAX發射機系統。此升頻混頻電路使用正交雙平衡架構,這裡使用兩個多相濾波器來產生需要的八相位震盪頻率訊號,此八相位產生器具有寬頻與低功率損耗的特性,混頻器方面利用了次諧波的技巧來降低內部震盪頻率遺漏至輸出的情況,而正交校正電路則整合在混頻電路的回授路徑來補償電路本身的不對稱,校正迴路中包括原本就會整合的高頻放大器、功率檢測器、低頻放大器、取樣維持比較器與補償電路,其中補償電路包括振幅與相位兩方面,兩者皆為不損耗功率並且省面積的電阻網路,可取代原先在混波器中的電阻,而不影響升頻混波器的效能。
    利用次諧波與正交校正的技巧,當使用0 dBm的輸入訊號作測試時,透過緩衝器量測到的載波頻率的遺漏量(LO leakage)可以壓制在相對於訊號源51 dBc以下,而不要的附帶頻段訊號壓制(sideband suppression)也可以在3.0 GHz至3.7 GHz的輸出頻率下,到達41 dBc以上的效果。升頻混波器電路本身在1.8 V的電壓下消耗10.4 mA的電流,分別有4 dB的訊號衰減,13.8 dBm的OIP3 (17 dBm IIP)與 3.9 dBm P1dB的特性。整個晶片面積為1.3 μm × 1.3 μm,其中包括升頻混波器電路,測試用的放大器電路,測試用的緩衝器電路,以及較正電路的部分。


    n this thesis, quadrature up-mixer circuits with sub-harmonic pumping technique and I/Q imbalance calibration loop are implemented in 0.18-μm mixed-mode CMOS technology for 3.5-GHz direct-conversion WiMAX transmitter applications. The mixer operates in quadrature double-balanced mode and require octet-phase (0°, 45°, 90°, 135°, 180°, 225°, 270°,and 315°) local oscillator (LO) signals which come from two polyphase filter circuits. For I/Q impairment cancellation, a calibration loop is integrated in the feedback path of the up-mixer circuits. The amplitude and phase compensation circuits of calibration loop are powerless and area efficiency resistor networks. Both can replace the original resistors in the up-mixer circuits and have no influence the up-mixer performance.
    By using sub-harmonic and I/Q calibration technique, the LO leakage at the measured buffer output can be suppressed more than 51 dBc below the fundamental tone with 0 dBm input power. For the sideband suppression, it is higher than 41 dBc from 3.0 GHz to 3.7 GHz. The quadrature up-mixer circuit consumes 10.4 mA from 1.8 V supply and shows -4 dB conversion loss, 13.8 dBm OIP3 (17 dBm IIP3) and 3.9 dBm P1dB, respectively. The total chip area including the up-mixer circuits, testing preamp, testing output buffer and calibration loop is 1.3 μm x 1.3 μm.

    Chapter 1 Introduction 1.1 Motivation 1.2 Transmitter Architecture 1.3 Thesis Organization Chapter 2 Quadrature Up-Mixer Overview 2.1 Up-Mixer Fundamentals 2.1.1 Conversion Gain 2.1.2 Noise Figure 2.1.3 1-dB Compression Point 2.1.4 Third-Order Intercept Point 2.1.5 Unwanted Sideband Cancellation 2.1.6 Unwanted Carrier Cancellation 2.2 Up-Mixer Topologies 2.2.1 Passive Mixer 2.2.2 Single Balanced Mixer 2.2.3 Double Balanced Mixer 2.2.4 Sub-Harmonic Mixer 2.3 Proposed Quadrature Up-Mixer Chapter 3 Quadrature Sub-Harmonic Up-Mixer Design 3.1 Octet-Phase LO Generator 3.1.1 Prior Art 3.1.2 Proposed Generator Circuit 3.2 LO Buffer 3.3 Quadrature Sub-Harmonic Up-Mixer 3.3.1 Driver Stage 3.3.2 Switching Stage 3.3.3 Power Combiner 3.4 Simulation Results 3.5 Summary Chapter 4 I/Q Mismatch Calibration Technique 4.1 I/Q Mismatch 4.2 Prior Calibration Techniques 4.3 Proposed Calibration Technique 4.3.1 Calibration Loop Topology 4.3.2 Calibration Circuit Design 4.3.3 Simulation Result 4.4 Summary Chapter 5 Design Implementation and Measurement 5.1 Design Implementation 5.2 Measurement Setup 5.3 Measurement Results of Test Chip 5.4 Measurement Results of Proposed Chips 5.5 Summary Chapter 6 Conclusions and Future Work 6.1 Conclusion 6.2 Future Work Appendix A.1 RF Power Detector A.2 Convergence of Calibration Loop

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