鐵酸鉍鐵電薄膜/鈦酸鍶鋇絕緣層/矽(MFIS)之特性

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研究生：	葉家修 Chia-Shiu Yeh
論文名稱：	鐵酸鉍鐵電薄膜/鈦酸鍶鋇絕緣層/矽(MFIS)之特性
指導教授：	吳振名 Jenn-Ming Wu
口試委員:
學位類別：	碩士 Master
系所名稱：	工學院 - 材料科學工程學系 Materials Science and Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	中文
論文頁數：	98
中文關鍵詞：	鐵酸鉍、鈦酸鍶鋇、記憶效應
相關次數：	點閱：3 下載：0
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摘要
隨著科技化時代的來臨，人類對於可攜式電子產品的需求越來越大，因此記憶體的演進受到廣大研究團隊的注目。其中鐵電記憶體屬於相當有發展潛力的一種非揮發性記憶體，隨著高積體密度、產品尺寸縮小化的影響，以MFIS場效電晶體作為主要結構的鐵電記憶體受到重視，此結構屬於非揮發性記憶體，具有高耐久度、低能耗，以及操作快速的特性，因此眾多候選材料皆不斷的被投入研究中，並針對其特性做研究分析。本實驗採用射頻磁控濺鍍法(rf-sputtering)在p-type矽基板上鍍製鈦酸鉛鋇絕緣層薄膜，並在其上再鍍製一層鐵酸鉍鐵鐵電薄膜，並藉由不同的熱處理溫度來改變其MFIS結構的記憶特性，希望藉此得到最佳的處理條件。在我們的實驗中，我們發現在經過攝氏五百度的氧氣氛熱處理後，可以使得記憶視窗有大幅的成長，可在±12V的掃描偏壓內得到約6.18V的記憶視窗值，原因在於此種熱處理條件可以使得氧化層與矽基板介面處的載子濃度降低約一個次方。而未來如能進一步掌握熱處理的細部參數，相信可以使得記憶特性有更進一步的成長。

目錄
摘要..................................................I
致謝.................................................II
目錄................................................III
表目錄..............................................VII
圖目錄..............................................VII

Chapter 1 前言
    記憶體簡介......................................1
    鐵電材料BiFeO3及高介電常數絕緣材料(Ba0.5Sr0.5)1.5TiO3
................................................2
Chapter 2 文獻回顧....................................5
2-1. FeRAM............................................5
2-1-1. 破壞性讀取與非破壞性讀取......................6
2-1-2. FeRAM的類型...................................7
2-1-3. 1T結構FeRAM的操作原則........................9
2-1-4. 現今1T結構FeRAM的發展瓶頸..................10
2-2. 鐵電材料.......................................12
2-3. 介電性質.......................................14
2-3-1. 極化機制.....................................14
2-3-2. 介電常數和散逸因子...........................16
2-3-3. 介電崩潰機制.................................16
2-3-4. 漏電流機制...................................17
2-4. BiFeO3特性介紹..................................19
2-4-1. 晶格結構......................................19
2-4-2. 優點..........................................20
2-4-3. 缺點..........................................21
2-5. 絕緣層於MFIS結構中之應用.......................22
2-5-1. 高介電常數(High-k)材料應用於絕緣體............22
2-6. (BaxSr1-x)TiO3(BST)特性介紹.......................24
Chapter 3 實驗流程...................................40
3-1. (BaxSr1-x)TiO3薄膜鍍製............................40
3-1-1. (BaxSr1-x)TiO3陶瓷靶材的製作....................40
3-1-2. 基板的準備....................................40
3-1-3. 鍍製Pt/BST/Si之MIS結構......................41
3-1-4. 鍍製白金上電極................................41
3-2. BiFeO3薄膜鍍製..................................41
3-2-1. BiFeO3陶瓷靶材的製作..........................41
3-2-2. 鍍製Pt/BFO/BST/Si之MFIS結構.................42
3-2-3. 薄膜熱處理....................................42
3-2-4. 鍍製白金上電極................................42
3-3. 薄膜之物性量測..................................42
3-3-1. XRD結晶繞射分析..............................42
3-3-2. SEM...........................................42
3-4. 薄膜之電性量測..................................42
3-4-1. I-V量測......................................42
3-4-2. C-V量測......................................43
3-4-3. Quasi C-V量測................................43
Chapter 4 結果討論...................................49
4-1. Pt/(Ba0.5Sr0.5)1.5TiO3/Si-MIS結構...................49
4-1-1. XRD pattern...................................49
4-1-2. SEM figure....................................49
4-1-3. I-V Characteristics...........................49
4-1-4. C-V Characteristics...........................50
4-2. Pt/BiFeO3/(Ba0.5Sr0.5)1.5TiO3/Si-MFIS結構............51
4-2-1. XRD pattern...................................51
4-2-2. SEM figure....................................52
4-2-3. AFM figure...................................53
4-2-4. I-V Characteristics..........................53
4-2-5. C-V Characteristics..........................54
4-2-5-1. C-V特性介紹...............................54
4-2-5-2. 記憶效應...................................55
4-2-6. 介電常數及tanδ...............................60
4-2-7. Qusai-CV量測及D_it運算........................61
4-2-8. C-V量測下鐵電薄膜的極化特性探討..............64
Chapter 5 結論......................................92
參考文獻............................................94










表目錄
Table 1-1鐵電材料的發展歷史.................. ......4
Table 2-1 PZT, SBT, BLT三種鐵電材料比較圖..........27
Table 2-3 各種漏電機制..............................30
Table 3-1 射頻磁控濺鍍機系統........................45
Table 3-2 BST薄膜鍍製參數..........................46
Table 3-3 Pt上電極鍍製參數.........................46
Table 3-4 BFO薄膜鍍製參數..........................48
圖目錄
Fig. 1-1 鈣鈦礦結構.................................4
Fig. 2-1 鐵電材料的P-E曲線.........................25
Fig. 2-2 MFIS FET記憶狀態示意.......................25
Fig. 2-3 MFMIS結構圖................................26
Fig. 2-4 All Epitaxial Perovskite FET...............26
Fig. 2-5 1T-2C FET及其二元極化方向..................27
Fig. 2-6 1T記憶體的操作及其記憶視窗特性.............28
Fig. 2-7 1T-FeRAM去極化場的機制.....................28
Fig. 2-8 閘極氧化層載子注入的機制...................29
Fig. 2-9 Perovskite結構之中心原子隨外加場移動示意圖.29
Fig. 2-10 鋯酸鉛鈦之相圖............................30
Fig. 2-11 四種極化機制..............................31
Fig. 2-12 不同極化機制對頻率的關係圖................32
Fig. 2-13 MIS結構的蕭特機發射能帶示意圖............32
Fig. 2-14 F-N tunneling示意圖......................33
Fig. 2-15 MIS結構的普爾-法蘭克發射能帶示意圖.......33
Fig. 2-16 BFO原子排列結構圖........................34
Fig. 2-17 BFO菱形與正方晶之原子排列示意圖..........35
Fig. 2-18 MIS結構中各種缺陷及陷阱..................35
Fig.3-1 BST陶瓷靶材的製備過程......................44
Fig.3-2 矽基板的清洗過程...........................45
Fig.3-3 BFO陶瓷靶材的製備過程......................47
Fig.3-4 MFIS電性量測示意圖.........................48
Fig.4-1 (Ba0.5Sr0.5)1.5TiO3/Si以低掠角掃描之X光繞射圖..68
Fig.4-2 (Ba0.5Sr0.5)1.5TiO3/Si 的SEM平面掃描圖.........68
Fig.4-3 (Ba0.5Sr0.5)1.5TiO3/Si的漏電曲線................69
Fig.4-4 (Ba0.5Sr0.5)1.5TiO3/Si的CV量測.................69
Fig.4-5 BiFeO3/(Ba0.5Sr0.5)1.5TiO3/Si的XRD..............70
Fig.4-6 BiFeO3/(Ba0.5Sr0.5)1.5TiO3/Si XRD比較...........70
Fig.4-7 BFO/BST/Si-as-deposited....................71
Fig.4-8 BFO/BST/Si-450℃-annealing.................71
Fig.4-9 BFO/BST/Si-500℃-annealing.................72
Fig.4-10 BFO/BST/Si-550℃-annealing................72
Fig.4-11 BFO/BST/Si的SEM切面圖...................73
Fig.4-12 BFO/BST/Si-as-deposited-AFM-2D圖.........74
Fig.4-13 BFO/BST/Si-as-deposited-AFM-3D圖.........74
Fig.4-14 BFO/BST/Si -450℃ annealing-AFM-2D圖.....75
Fig.4-15 BFO/BST/Si -450℃ annealing-AFM-3D圖.....75
Fig.4-16 BFO/BST/Si -500℃ annealing-AFM-2D圖.....76
Fig.4-17 BFO/BST/Si -500℃ annealing-AFM-3D圖.....76
Fig.4-18 BFO/BST/Si -550℃ annealing-AFM-2D圖.....77
Fig.4-19 BFO/BST/Si -550℃ annealing-AFM-3D圖.....77
Fig.4-20 BFO/BST/Si四種條件下的漏電曲線...........78
Fig.4-21 BFO/BST/Si -as deposited-CV曲線..........78
Fig.4-22 BFO/BST/Si -450℃ annealing-CV曲線.......79
Fig.4-23 BFO/BST/Si -500℃ annealing-CV曲線.......79
Fig.4-24 BFO/BST/Si -550℃ annealing-CV曲線.......80
Fig.4-25 BFO/BST/Si -as deposited- Vf,Vr,Vm.........80
Fig.4-26 BFO/BST/Si -450℃annealing- Vf,Vr,Vm.......81
Fig.4-27 BFO/BST/Si -500℃annealing- Vf,Vr,Vm.......81
Fig.4-28 BFO/BST/Si -550℃annealing- Vf,Vr,Vm.......82
Fig.4-29 BFO/BST/Si四個條件下的記憶視窗比較.......82
Fig.4-30 BFO/BST/Si -as deposited-CV偏移..........83
Fig.4-31 Pt/BiFeO3/Pt –介電常數...................83
Fig.4-32 Pt/BiFeO3/Pt –tanδ......................84
Fig.4-33 Dit量測簡示..............................84
Fig.4-34 電容值校正的示意圖.......................85
Fig.4-35 電容值校正與Quasi比較圖.................86
Fig.4-36 BFO/BST/Si-as deposited-Dit..............86
Fig.4-37 BFO/BST/Si -450℃annealing-Dit...........87
Fig.4-38 BFO/BST/Si -500℃annealing-Dit...........87
Fig.4-39 BFO/BST/Si -550℃annealing-Dit...........88
Fig.4-40 BiFeO3 MFM-as deposited-PE curve............88
Fig.4-41 BiFeO3 MFM-450℃ annealing-PE curve.........89
Fig.4-42 BiFeO3 MFM-500℃ annealing-PE curve.........89
Fig.4-43 BiFeO3 MFM-550℃ annealing-PE curve.........90
Fig. 4-44 BiFeO3 MFM-Pr比較..........................90
Fig. 4-44 BiFeO3 MFM-Ec比較..........................91
Fig. 4-45 BiFeO3 MFM-漏電比較........................91

                                

參考文獻
[1]- 高明哲 “非揮發性記憶體(NVM)，相變化記憶體(PCM)”
[2]- J. M. Lee, K. T. Kim, and C. I. Kim “Characteristics of Pt/Bi3.25La0.75Ti3O12/ZrO2/Si structure using ZrO2 as buffer layers for ferroelectric gate field effect transistors” J. Vac. Sci. Technol. A, 22, No. 4 (2004)
[3]- D. Ito, T. Yoshimura, N. Fujimura, T. Ito “Improvement of Y2O3/Si interface for FeRAM application” Applied Surface Science, 159-160, 138-142 (2000)
[4]- E. Tokumitsu, T. Isobe, T. Kijima, and H. Ishiwara “Fabrication and characterization of Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFIS) structures using ferroelectric (Bi, La)4Ti3O12 films” Jpn. J. Appl. Phys., 40, 5576 (2001)
[5]- A. G. Schrott and J. A. Misewich “Ferroelectric field-effect transistor with a SrRuxTi1-xO3 channel” Appl. Phys. Lett., 82, 4770 (2003)
[6]- S. Mathews, R. Ramesh, T. Venkatesan, and J. Benedetto “Ferroelectric field effect transistor based on epitaxial perovskite heterostructures”SCIENCE, 276, 238 (1997)
[7]- S. M. Yoon, and H. Ishiwara “Memory operations of 1T2C-type ferroelectric memory cell with excellent data retention characteristics” IEEE Trans. Electron. Dev., 48, 2002 (2001)
[8]- H. Ishiwara “Recent progress of FET-Type ferroelectric memories” IEDM, 263 (2003)
[9]- M. Noda, K. Kodama, S. Kitai, M. Takahashi, T. Kanashima, and M. Okuyama “Basic characteristics of Metal-Ferroelectric-Insulator-Semiconductor structure using a high-k PrOx insulator layer” Jpn. Appl. Phys., 93, 4137 (2003)
[10]- E. Tokmitsu, G. Fujii, and H. Ishiwara “Nonvolatile ferroelectric-gate field-effect transistors using Pt/SrBi2Ta2O9/SrTa2O6/SiON/Si structures” Appl. Phys. Lett., 75, 575 (1999)
[11]- I. Takahashi, H. Sakurai, and T. Isogai “MFIS structure device with a low dielectric constant ferroelectric Sr2(Ta1-xNbx)2O7 formed by plasma physical vapor deposition and oxygen radical treatment” Integrated Ferroelectric, 65, 29 (2004)
[12]- T. P. Ma and J. P. Han “Why is Nonvolatile Ferroelectric Memory Field-Effect Transistor Still Elusive?” IEEE Electron Dev. Lett., 23, 386 (2002)
[13]- N. Fujimura, and T. Yoshimura “Preparation and properties of ferroelectric-insulator-semiconductor junctions using YMnO3 thin films” Appl. Phys. Lett., 98, 199 (2005)
[14]- K. Aizawa, T. Okamoto, and E. Tokumitsu “Fabraication and characterization of metal-ferroelectrics-semiconductor field effect transistor using epitaxial BaMgF4 films grown on Si(111) substrates” Integrated Ferroelectrics, 15, 245 (1997)
[15]- K. H. Kim “Metal-ferroelectric-semiconductor(MFS) FETs using LiNbO3/Si(100) structures for nonvolatile memory application” IEEE Electron Dev. Lett., 19, 204 (1998)
[16]- F. Y. Zhang, S. T. Hsu, and Y. Ono “Fabrication and characterization of sub-micron metal-ferroelectric-insulator-semiconductor field effect transistors with Pt/Pb5Ge3O11/ZrO2/Si structure” Jpn. Appl. Phys., 40, 635 (2001)
[17]- T. Nakaiso, M. Noda, and M. Okuyama “Low-temperature preparation of ferroelectric Sr2(Ta1-xNbx)xO7 thin films by pulsed laser deposition and their application to metal-ferroelectric-insulator-semiconductor FET” Jpn. J. Appl. Phys., 40, 2935 (2001)
[18]- B. Jaffe, W. R. Cooke Jr., and H. Jaffe “Piezoelectric Ceramics” Academic Press, New York (1971)
[19]- J. F. Scott, C. A. Araujo, B. M. Melnick, L. D. McMillan, and R. Zuleeg “Quantitative measurement of space-charge effects in lead zirconate-titanate memories” Jpn. Appl. Phys., 70, 382 (1991)
[20]- M. Dawber, J. F. Scott “A model for fatigue in ferroelectric perovskite thin films” Appl. Phys. Lett., 76, 1060 (2000)
[21]- A. J. Moulson and J. M. Herbert “Electroceramics materials properties and application” p.52-55 and p.61-62 (1990)
[22]- 李雅明, “固態電子學” 全華科技 (1995)
[23]- 吳朗, “電子陶瓷-介電” 全新資訊圖書 (1994)
[24]- 施修正, “利用濺鍍法以鎳酸鑭為電極製作動態記憶體之鈦酸鋇薄膜的研究” 清華大學博士論文 (1999)
[25]- Y. S. Yang, S. J. Lee, S. H. Kim, B. G. Chae, and M. S. Jang “Schottky barrier effects in the electronic conduction of sol-gel derived lead zirconate titanate thin film capacitors” Jpn. Appl. Phys., 84, 5005-5011 (1998)
[26]- I. Stolichnov, and A. Tagantsev “Space-charge influenced-injection model for conduction on Pb(ZrxTi1-x)O3 thin films” Jpn. Appl. Phys., 84, 3216-3225 (1998)
[27]- J. Wang, J. B. Neaton, H. Zheng, V. Nagarajan , S. B.Ogale, B. Liu, D. Viehland, V. Vaithyanathan, D. G. Schlom, U. V. Waghmare, N. A. Spaldin, K. M. Rabe, M.Wuttig, and R. Ramesh “Epitaxial BiFeO3 multiferroic thin film heterostructures” Science, 299, 1719 (2003)
[28]- F. Kubel and H. Schmid：Acta Crystallography, Sect., B46, 698 (1990)
[29]- K. Y. Yun, D. Richinschi, T. Kanashima, M. Noda, and M. Okuyama “Giant ferroelectric polarization beyond 150μC/cm2 in BiFeO3 thin film” Jpn. Appl. Phys., 43, L647 (2004)
[30]- Y. P. Wang, L. zhou, M.F. Zhang, X. Y. Chen, J. M. Liu, and Z. G. Liu “Room-temperature saturated ferroelectric polarization in BiFeO3 ceramics synthesized by rapid liquid phase sintering” Appl. Phys. Lett., 84, 1731 (2004)
[31]- B. Ruette, S. Zvyagin, A. P. Pyatakov, A. Bush, J. F. Li, V. I. Beotelov, A. K. Zvezdin, and D. Viehland “Magnetic-field-induced phase trasition in BiFeO3 observed by high-field electron spin resonance: Cycloidal to homogeneous spin order” Phys. Rev., B69, 064114 (2004)
[32]- J. F. Scott “Ferroelectric Memories” chap. 12
[33]- B. E. Park, S. Shouriki, E. Tokumitsu, and H. Ishiwara “Fabrication of PbZrxTi1-xO3 films on silicon substrates using Y2O3 buffer layers” Jpn. J. Appl. Phys., 37, 5145 (1998)
[34]- L. A. Ragnarsson, S. Guha, N. A. Bojarczuk, E.Cartier, M. V. Fischetti, K. Rim, and J. Karasinski “Electrical characterization of Al2O3 n-channel MOSFETs with aluminum gates” IEEE Electron Dev. Lett., vol.2, 490 (2001)
[35]- L. Kwo, M. Hong, A. R. Kortan, K. T. Queeney, Y. J. Chabal, J. P. Mannaerts, T. Boone, J. J. Krajewski, A. M. Sergent, and J. M. Rosamilia “High-k gate dielectrics Gd2O3 and Y2O3 for silicon” Appl. Phys. Lett. 77, 130 (2000)
[36]- B. H. Lee, R. Choi, L. Kang, S. Gopalan, R. Nieh, K. Onishi, Y. Jeon, W. J. Qi, C. Kang, and J. C. Lee “Characteristics of TaN gate MOSFET with hafnium oxide(8□-12□)” IEDM, 39 (2000)
[37]- A. Callegari, E. Cartier, M. Gribelyuk, H. F. Okorn-Schmidt, and T. Zabel “Physical and electrical characterization of hafnium oxide and hafnium silicate sputtered films” Jpn. Appl. Phys., 90, 6466 (2001)
[38]- P. C. Juan, C. Y. Chang, and Y. M. Lee “A New Metal- Ferroelectric(PbZr0.53Ti0.47O3)- Insulator(Dy2O3)- Semiconductor(MFIS) FET for nonvolatile memory applications”IEEE Electron Dev. Lett., vol.27, 217 (2006)
[39]- M. Copel, M. A. Gribelyuk, and E. Gusev “Structure and stability of ultrathin zirconium oxide layers on Si(001)” Appl. Phys. Lett., 76, 436 (2000)
[40]- H. F. Luan, S. J. Lee, C. H. Lee, S. C. Song, Y. L. Mao, Y.Senzaki, D. Roberts, and D. L. Kwong “High quality Ta2O5 gate dielectrics with Tox<10□” IEDM, 141 (1999)
[41]- R. Droopad, Z. Yu, J. Ramdani, L. Hilt, J. Curless, C. Overgaard, J. L. Edwards, J. Finder, K. Eisenbeiser, J. Wang, V. Kaushik, B. Y. Ngyuen, B. Ooms “Epitaxial oxides on silicon grown by molecular beam epitaxy” J. Crys. Growth, 936 (2001)
[42]- S. A. Chambers, Y. Liang, Z. Yu, R. Droopad, J. Ramdani, and K. Eisenbeiser “Band discontinuities at epitaxial SrTiO3 on Si(001) heterojunctions” Appl. Phys. Lett., 77, 1662 (2000)
[43]- G. D. Wilk, R. M. Wallace, and J. M. Anthony “High-k gate dielectrics: Current status and materials properties considerations” Jpn. Appl. Phys., 85, 5243 (2001)
[44]- Dieter K. Schroder “Semiconductor material and device characterization 2ND edition” p349
[45]- S. L. Miller and P. J. McWhorter “Physics of ferroelectric nonvolatile memory field effect transistor” J. Appl. Phys., 72, 5999 (1992)
[46]- K. S. K. Kwa, S. Chattopadhyay, N. D. Jankovic, S. H. Olsen, L. S. Driscoll, and A. G. O'Neill “A model for capacitance reconstruction from measured lossy MOS capacitance-voltage characteristics” Semiconductor Science and Technol., 18, 82 (2003)
[47]- Z. Xu, L. Goux, B. Kaczer, H. V. Meeren, D. J. Wouters, and G. Groeseneken “Relevance of the pulsed capacitance voltage measurement thchnique for the optimization of SrBi2Ta2O9 high k stack combination to be used in FeFET devices” Microelectronic Engin. 83, 2564 (2006)

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